Line data Source code
1 : /**
2 : * Copyright (c) 2025 Huawei Technologies Co., Ltd.
3 : * This program is free software, you can redistribute it and/or modify it under the terms and conditions of
4 : * CANN Open Software License Agreement Version 2.0 (the "License").
5 : * Please refer to the License for details. You may not use this file except in compliance with the License.
6 : * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR IMPLIED,
7 : * INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY, OR FITNESS FOR A PARTICULAR PURPOSE.
8 : * See LICENSE in the root of the software repository for the full text of the License.
9 : */
10 :
11 : #include "runtime/base.h"
12 : #include "dump_common.h"
13 : #include "register_config.h"
14 : #include "acc_error_info.h"
15 : #include "adump_platform_manager.h"
16 : #include "log/adx_log.h"
17 :
18 : namespace Adx {
19 :
20 185 : const std::vector<RegisterTable>& RegisterInterface::GetRegisterTable(RegisterType type) const
21 : {
22 185 : static std::vector<RegisterTable> defaultTables = {};
23 185 : return registerTableMap_.find(type) != registerTableMap_.end() ? registerTableMap_.at(type) : defaultTables;
24 : }
25 :
26 89 : const std::vector<RegisterType>& RegisterInterface::GetRegisterTypes(uint8_t coreType) const
27 : {
28 89 : static std::vector<RegisterType> defaultTypes = {};
29 89 : return registerTypeMap_.find(coreType) != registerTypeMap_.end() ? registerTypeMap_.at(coreType) : defaultTypes;
30 : }
31 :
32 88 : const std::vector<ErrorRegisterTable>& RegisterInterface::GetErrorRegisterTable() const { return ErrorRegisterMap_; }
33 :
34 10 : CloudV2Register::CloudV2Register()
35 : {
36 : registerTableMap_ = {
37 0 : {RegisterType::SU,
38 : {{GetAddr(0, 0), 32, 8}, // GPR0 - GPR31
39 : {GetAddr(0, 64), 1, 8}, // PC
40 : {GetAddr(0, 66), 8, 8}, // 66-73
41 : {GetAddr(0, 75), 4, 8}, // 75-78
42 : {GetAddr(0, 128), 12, 8}}}, // 128-139
43 0 : {RegisterType::VEC,
44 : {{GetAddr(256, 0), 2, 16}, // MASK CMPMASK
45 : {GetAddr(256, 2), 14, 8}, // 2-15
46 : {GetAddr(257, 0), 8, 16}}}, // VARF0 - VARF7
47 0 : {RegisterType::MTE,
48 : {{GetAddr(515, 0), 17, 8}, // 0-16
49 : {GetAddr(515, 23), 25, 8}}}, // AIPP_SPR_0 - AIPP_SPR_24
50 0 : {RegisterType::CUBE,
51 : {{GetAddr(768, 0), 1, 8}, // LOW_PRE_TBL
52 : {GetAddr(768, 0x2000), 1, 8}, // SMASK_INDEX
53 : {GetAddr(768, 0x4000), 1, 8}}}, // FIXP_PRE_BUF
54 100 : };
55 : registerTypeMap_ = {
56 : {CORE_TYPE_AIC, {RegisterType::SU, RegisterType::MTE, RegisterType::CUBE, RegisterType::BIU}},
57 40 : {CORE_TYPE_AIV, {RegisterType::SU, RegisterType::VEC, RegisterType::BIU}}};
58 : ErrorRegisterMap_ = {
59 20 : {RT_V100_AIC_ERR_0, 0x00000700, 4, "AIC_ERROR_0"}, {RT_V100_AIC_ERR_1, 0x00000704, 4, "AIC_ERROR_1"},
60 10 : {RT_V100_AIC_ERR_2, 0x00000760, 4, "AIC_ERROR_2"}, {RT_V100_AIC_ERR_3, 0x00000764, 4, "AIC_ERROR_3"},
61 10 : {RT_V100_AIC_ERR_4, 0x00000780, 4, "AIC_ERROR_4"}, {RT_V100_AIC_ERR_5, 0x00000790, 4, "AIC_ERROR_5"},
62 10 : {RT_V100_BIU_ERR_0, 0x00000710, 4, "BIU_ERR_INFO_0"}, {RT_V100_BIU_ERR_1, 0x00000714, 4, "BIU_ERR_INFO_1"},
63 10 : {RT_V100_CCU_ERR_0, 0x00000718, 4, "CCU_ERR_INFO_0"}, {RT_V100_CCU_ERR_1, 0x0000071C, 4, "CCU_ERR_INFO_1"},
64 10 : {RT_V100_IFU_ERR_0, 0x00000728, 4, "IFU_ERR_INFO_0"}, {RT_V100_IFU_ERR_1, 0x0000072C, 4, "IFU_ERR_INFO_1"},
65 10 : {RT_V100_MTE_ERR_0, 0x00000730, 4, "MTE_ERR_INFO_0"}, {RT_V100_MTE_ERR_1, 0x00000734, 4, "MTE_ERR_INFO_1"},
66 10 : {RT_V100_VEC_ERR_0, 0x00000738, 4, "VEC_ERR_INFO_0"}, {RT_V100_VEC_ERR_1, 0x0000073C, 4, "VEC_ERR_INFO_1"},
67 10 : {RT_V100_FIXP_ERR_0, 0x0000078C, 4, "FIXP_ERR_INFO_0"}, {RT_V100_FIXP_ERR_1, 0x000007C8, 4, "FIXP_ERR_INFO_1"},
68 10 : {RT_V100_CUBE_ERR_0, 0x00000720, 4, "CUBE_ERR_INFO"},
69 200 : };
70 100 : }
71 :
72 130 : uint64_t CloudV2Register::GetAddr(uint64_t regAddrHigh, uint64_t regAddrLow) const
73 : {
74 130 : return (regAddrHigh << HIGH_ADDR_SHIFT) | regAddrLow;
75 : }
76 :
77 : // 基类只提供地址生成工具，不预置版本专属排列：Debug 寄存器排列各版本不同，由派生类自行初始化。
78 16 : CloudBaseRegister::CloudBaseRegister() = default;
79 :
80 12 : CloudV4Register::CloudV4Register()
81 : {
82 12 : GenAICDbgAddr();
83 12 : GenAIVDbgAddr();
84 12 : GenAICOffsetAddr();
85 12 : GenAIVOffsetAddr();
86 : registerTypeMap_ = {
87 : {CORE_TYPE_AIC, {RegisterType::AIC, RegisterType::AIC_DBG}},
88 48 : {CORE_TYPE_AIV, {RegisterType::AIV, RegisterType::AIV_DBG}}};
89 12 : InitErrorRegisterMap();
90 48 : }
91 :
92 12 : void CloudV4Register::InitErrorRegisterMap()
93 : {
94 : ErrorRegisterMap_ = {
95 12 : {RT_V200_SC_ERROR_T0_0, 0x4700, 4, "SC_ERROR_T0_0"},
96 12 : {RT_V200_SC_ERR_INFO_T0_0, 0x4730, 4, "SC_ERR_INFO_T0_0"},
97 12 : {RT_V200_SC_ERR_INFO_T0_1, 0x4734, 4, "SC_ERR_INFO_T0_1"},
98 12 : {RT_V200_SU_ERROR_T0_0, 0x5700, 4, "SU_ERROR_T0_0"},
99 12 : {RT_V200_SU_ERR_INFO_T0_0, 0x5730, 4, "SU_ERR_INFO_T0_0"},
100 12 : {RT_V200_SU_ERR_INFO_T0_1, 0x5734, 4, "SU_ERR_INFO_T0_1"},
101 12 : {RT_V200_SU_ERR_INFO_T0_2, 0x5738, 4, "SU_ERR_INFO_T0_2"},
102 12 : {RT_V200_SU_ERR_INFO_T0_3, 0x573C, 4, "SU_ERR_INFO_T0_3"},
103 12 : {RT_V200_MTE_ERROR_T0_0, 0x6700, 4, "MTE_ERROR_T0_0"},
104 12 : {RT_V200_MTE_ERROR_T1_0, 0x6708, 4, "MTE_ERROR_T1_0"},
105 12 : {RT_V200_MTE_ERR_INFO_T0_0, 0x6718, 4, "MTE_ERR_INFO_T0_0"},
106 12 : {RT_V200_MTE_ERR_INFO_T0_1, 0x671C, 4, "MTE_ERR_INFO_T0_1"},
107 12 : {RT_V200_MTE_ERR_INFO_T0_2, 0x6720, 4, "MTE_ERR_INFO_T0_2"},
108 12 : {RT_V200_MTE_ERR_INFO_T1_0, 0x6724, 4, "MTE_ERR_INFO_T1_0"},
109 12 : {RT_V200_MTE_ERR_INFO_T1_1, 0x6728, 4, "MTE_ERR_INFO_T1_1"},
110 12 : {RT_V200_MTE_ERR_INFO_T1_2, 0x673C, 4, "MTE_ERR_INFO_T1_2"},
111 12 : {RT_V200_VEC_ERROR_T0_0, 0x7700, 4, "VEC_ERROR_T0_0"},
112 12 : {RT_V200_VEC_ERROR_T0_2, 0x7708, 4, "VEC_ERROR_T0_2"},
113 12 : {RT_V200_VEC_ERR_INFO_T0_0, 0x7730, 4, "VEC_ERR_INFO_T0_0"},
114 12 : {RT_V200_VEC_ERR_INFO_T0_1, 0x7734, 4, "VEC_ERR_INFO_T0_1"},
115 12 : {RT_V200_VEC_ERR_INFO_T0_2, 0x7738, 4, "VEC_ERR_INFO_T0_2"},
116 12 : {RT_V200_VEC_ERR_INFO_T0_3, 0x773C, 4, "VEC_ERR_INFO_T0_3"},
117 12 : {RT_V200_VEC_ERR_INFO_T0_4, 0x7740, 4, "VEC_ERR_INFO_T0_4"},
118 12 : {RT_V200_VEC_ERR_INFO_T0_5, 0x7744, 4, "VEC_ERR_INFO_T0_5"},
119 12 : {RT_V200_CUBE_ERROR_T0_0, 0x8700, 4, "CUBE_ERROR_T0_0"},
120 12 : {RT_V200_CUBE_ERROR_T0_1, 0x8704, 4, "CUBE_ERROR_T0_1"},
121 12 : {RT_V200_CUBE_ERR_INFO_T0_0, 0x8730, 4, "CUBE_ERR_INFO_T0_0"},
122 12 : {RT_V200_CUBE_ERR_INFO_T0_1, 0x8734, 4, "CUBE_ERR_INFO_T0_1"},
123 12 : {RT_V200_L1_ERROR_T0_0, 0xA700, 4, "L1_ERROR_T0_0"},
124 12 : {RT_V200_L1_ERROR_T0_1, 0xA704, 4, "L1_ERROR_T0_1"},
125 12 : {RT_V200_L1_ERR_INFO_T0_0, 0xA718, 4, "L1_ERR_INFO_T0_0"},
126 12 : {RT_V200_L1_ERR_INFO_T0_1, 0xA71C, 4, "L1_ERR_INFO_T0_1"},
127 396 : };
128 36 : }
129 :
130 12 : void CloudBaseRegister::GenAICDbgAddr()
131 : {
132 : std::vector<RegisterTable> regAICDbgTab = {
133 : // SU(for AIC)
134 : {0X10000000000000, 32, 8},
135 : {0X10000000000040, 15, 8},
136 : {0X10000000000080, 12, 8},
137 : {0X15000000000000, 32, 8},
138 : {0X15800000000000, 32, 8},
139 : {0X16000000000000, 16, 8},
140 : {0X16800000000000, 32, 8},
141 : // MTE(for AIC)
142 : {0X21000000000000, 1, 8},
143 : {0X22000000000000, 2, 8},
144 : {0X22000000000003, 4, 8},
145 : {0X22000000000012, 1, 8},
146 : {0X24000000000014, 1, 8},
147 : // CUBE
148 : {0X40000000000000, 8, 8},
149 : {0X40000000000008, 8, 8},
150 : {0X40000000000010, 8, 8},
151 : {0X40000000000018, 8, 8},
152 : {0X40000000000020, 8, 8},
153 : {0X40000000000028, 8, 8},
154 : {0X40000000000030, 8, 8},
155 : {0X40000000000038, 8, 8},
156 : {0X40000000000040, 8, 8},
157 : {0X40000000000048, 8, 8},
158 : {0X40000000000050, 8, 8},
159 : {0X40000000000058, 8, 8},
160 : {0X40000000000060, 8, 8},
161 : // L1
162 : {0X60000000000000, 10, 8},
163 : {0X61000000000000, 11, 8},
164 : {0X67000000000000, 1, 8},
165 : // others
166 : {0X80000000000000, 5, 8},
167 : {0X90000000000000, 9, 8},
168 : {0X90000000000040, 8, 8},
169 : {0X90000000000080, 13, 8},
170 : {0X900000000000c0, 8, 8},
171 : {0Xa0000000000000, 3, 8},
172 : {0Xa0000000000100, 3, 8},
173 : {0Xa0000000000200, 3, 8},
174 : {0Xa0000000001000, 1, 8},
175 : {0Xa0000000001100, 1, 8},
176 : {0Xa0000000001200, 1, 8},
177 : {0Xa0000000002100, 2, 8},
178 : {0Xa0000000002200, 2, 8},
179 : {0Xa0000000003000, 1, 8},
180 : {0Xa0000000008100, 3, 8},
181 : {0Xc0000000000000, 16, 8},
182 : {0Xd0000000000000, 1, 8},
183 : {0Xd0000000000008, 1, 8},
184 : {0Xd0000000000010, 1, 8},
185 : {0Xd0000000000018, 1, 8},
186 : {0Xd0000000000020, 1, 8},
187 : {0Xd0000000000028, 1, 8},
188 : {0Xd0000000000030, 1, 8},
189 : {0Xd0000000000038, 1, 8},
190 : {0Xe0000000000000, 5, 8},
191 : {0Xe0000000000100, 3, 8},
192 : {0Xe0000000000200, 6, 8},
193 : {0Xe0000000000300, 2, 8},
194 : {0Xe0000000000400, 1, 8},
195 : {0Xe0000000000500, 9, 8},
196 : {0Xe0000000000600, 16, 8},
197 24 : };
198 12 : registerTableMap_[RegisterType::AIC_DBG] = regAICDbgTab;
199 12 : }
200 :
201 12 : void CloudBaseRegister::GenAIVDbgAddr()
202 : {
203 12 : std::vector<RegisterTable> regAIVDbgTab;
204 12 : auto suTab = GenAIVDbgSUAddr();
205 12 : auto mteTab = GenAIVDbgMTEAddr();
206 12 : auto vecRbTab = GenAIVDbgVECRBAddr();
207 12 : auto othersTab = GenAIVDbgOthersAddr();
208 24 : regAIVDbgTab.insert(regAIVDbgTab.end(), suTab.begin(), suTab.end());
209 24 : regAIVDbgTab.insert(regAIVDbgTab.end(), mteTab.begin(), mteTab.end());
210 24 : regAIVDbgTab.insert(regAIVDbgTab.end(), vecRbTab.begin(), vecRbTab.end());
211 24 : regAIVDbgTab.insert(regAIVDbgTab.end(), othersTab.begin(), othersTab.end());
212 12 : registerTableMap_[RegisterType::AIV_DBG] = regAIVDbgTab;
213 12 : }
214 :
215 4 : CloudV5Register::CloudV5Register()
216 : {
217 : // V5 Debug 排列与 V4 不同，暂未适配，registerTableMap_/registerTypeMap_ 有意留空待后续开发：
218 : // 留空使 Debug 循环空转，避免按 V4 排列读 V5 地址产出错误数据；错误寄存器不受影响。
219 4 : IDE_LOGW("[DumpCore] CloudV5 debug register layout is not adapted yet, "
220 : "coredump will contain error registers only.");
221 4 : InitErrorRegisterMap();
222 4 : }
223 :
224 4 : void CloudV5Register::InitErrorRegisterMap()
225 : {
226 : ErrorRegisterMap_ = {
227 4 : {RT_V200_SC_ERROR_T0_0, 0x4700, 4, "SC_ERROR_T0_0"},
228 4 : {RT_V200_SC_ERR_INFO_T0_0, 0x4730, 4, "SC_ERR_INFO_T0_0"},
229 4 : {RT_V200_SC_ERR_INFO_T0_1, 0x4734, 4, "SC_ERR_INFO_T0_1"},
230 4 : {RT_V200_SU_ERROR_T0_0, 0x5700, 4, "SU_ERROR_T0_0"},
231 4 : {RT_V200_SU_ERROR_T0_1, 0x5704, 4, "SU_ERROR_T0_1"},
232 4 : {RT_V200_SU_ERR_INFO_T0_0, 0x5730, 4, "SU_ERR_INFO_T0_0"},
233 4 : {RT_V200_SU_ERR_INFO_T0_1, 0x5734, 4, "SU_ERR_INFO_T0_1"},
234 4 : {RT_V200_SU_ERR_INFO_T0_2, 0x5738, 4, "SU_ERR_INFO_T0_2"},
235 4 : {RT_V200_SU_ERR_INFO_T0_3, 0x573C, 4, "SU_ERR_INFO_T0_3"},
236 4 : {RT_V200_SU_ERR_INFO_T0_4, 0x5740, 4, "SU_ERR_INFO_T0_4"},
237 4 : {RT_V200_SU_ERR_INFO_T0_5, 0x5744, 4, "SU_ERR_INFO_T0_5"},
238 4 : {RT_V200_SU_ERR_INFO_T0_6, 0x5748, 4, "SU_ERR_INFO_T0_6"},
239 4 : {RT_V200_SU_ERR_INFO_T0_7, 0x574C, 4, "SU_ERR_INFO_T0_7"},
240 4 : {RT_V200_MTE_ERROR_T0_0, 0x6700, 4, "MTE_ERROR_T0_0"},
241 4 : {RT_V200_MTE_ERROR_T1_0, 0x6708, 4, "MTE_ERROR_T1_0"},
242 4 : {RT_V200_MTE_ERR_INFO_T0_0, 0x6718, 4, "MTE_ERR_INFO_T0_0"},
243 4 : {RT_V200_MTE_ERR_INFO_T0_1, 0x671C, 4, "MTE_ERR_INFO_T0_1"},
244 4 : {RT_V200_MTE_ERR_INFO_T0_2, 0x6720, 4, "MTE_ERR_INFO_T0_2"},
245 4 : {RT_V200_MTE_ERR_INFO_T1_0, 0x6724, 4, "MTE_ERR_INFO_T1_0"},
246 4 : {RT_V200_MTE_ERR_INFO_T1_1, 0x6728, 4, "MTE_ERR_INFO_T1_1"},
247 4 : {RT_V200_MTE_ERR_INFO_T1_2, 0x673C, 4, "MTE_ERR_INFO_T1_2"},
248 4 : {RT_V200_VEC_ERROR_T0_0, 0x7700, 4, "VEC_ERROR_T0_0"},
249 4 : {RT_V200_VEC_ERROR_T0_2, 0x7708, 4, "VEC_ERROR_T0_2"},
250 4 : {RT_V200_VEC_ERR_INFO_T0_0, 0x7730, 4, "VEC_ERR_INFO_T0_0"},
251 4 : {RT_V200_VEC_ERR_INFO_T0_1, 0x7734, 4, "VEC_ERR_INFO_T0_1"},
252 4 : {RT_V200_VEC_ERR_INFO_T0_2, 0x7738, 4, "VEC_ERR_INFO_T0_2"},
253 4 : {RT_V200_VEC_ERR_INFO_T0_3, 0x773C, 4, "VEC_ERR_INFO_T0_3"},
254 4 : {RT_V200_VEC_ERR_INFO_T0_4, 0x7740, 4, "VEC_ERR_INFO_T0_4"},
255 4 : {RT_V200_VEC_ERR_INFO_T0_5, 0x7744, 4, "VEC_ERR_INFO_T0_5"},
256 4 : {RT_V200_VEC_ERR_INFO_T0_6, 0x7748, 4, "VEC_ERR_INFO_T0_6"},
257 4 : {RT_V200_CUBE_ERROR_T0_0, 0x8700, 4, "CUBE_ERROR_T0_0"},
258 4 : {RT_V200_CUBE_ERROR_T0_1, 0x8704, 4, "CUBE_ERROR_T0_1"},
259 4 : {RT_V200_CUBE_ERR_INFO_T0_0, 0x8730, 4, "CUBE_ERR_INFO_T0_0"},
260 4 : {RT_V200_CUBE_ERR_INFO_T0_1, 0x8734, 4, "CUBE_ERR_INFO_T0_1"},
261 4 : {RT_V200_L1_ERROR_T0_0, 0xA700, 4, "L1_ERROR_T0_0"},
262 4 : {RT_V200_L1_ERROR_T0_1, 0xA704, 4, "L1_ERROR_T0_1"},
263 4 : {RT_V200_L1_ERR_INFO_T0_0, 0xA718, 4, "L1_ERR_INFO_T0_0"},
264 4 : {RT_V200_L1_ERR_INFO_T0_1, 0xA71C, 4, "L1_ERR_INFO_T0_1"},
265 156 : };
266 12 : }
267 12 : std::vector<RegisterTable> CloudBaseRegister::GenAIVDbgSUAddr()
268 : {
269 : return {
270 : {0X10000000000000, 32, 8}, {0X10000000000040, 15, 8}, {0X10000000000080, 12, 8}, {0X15000000000000, 32, 8},
271 : {0X15800000000000, 32, 8}, {0X16000000000000, 16, 8}, {0X16800000000000, 16, 8},
272 36 : };
273 : }
274 :
275 12 : std::vector<RegisterTable> CloudBaseRegister::GenAIVDbgMTEAddr()
276 : {
277 : return {
278 : {0X21000000000000, 1, 8},
279 : {0X22000000000002, 1, 8},
280 : {0X22000000000007, 3, 8},
281 : {0X2200000000000d, 3, 8},
282 36 : {0X22000000000016, 9, 8}};
283 : }
284 :
285 12 : std::vector<RegisterTable> CloudBaseRegister::GenAIVDbgVECRBAddr()
286 : {
287 : return {{0X32000000000000, 8, 32}, {0X32000000000010, 8, 32}, {0X32000000000020, 8, 32},
288 : {0X32000000000030, 8, 32}, {0X32000000000040, 8, 32}, {0X32000000000050, 8, 32},
289 : {0X32000000000060, 8, 32}, {0X32000000000070, 8, 32}, {0X32000000000080, 8, 32},
290 : {0X32000000000090, 8, 32}, {0X320000000000a0, 8, 32}, {0X320000000000b0, 8, 32},
291 : {0X320000000000c0, 8, 32}, {0X320000000000d0, 8, 32}, {0X320000000000e0, 8, 32},
292 : {0X320000000000f0, 8, 32}, {0X32000000000100, 8, 32}, {0X32000000000110, 8, 32},
293 : {0X32000000000120, 8, 32}, {0X32000000000130, 8, 32}, {0X32000000000140, 8, 32},
294 : {0X32000000000150, 8, 32}, {0X32000000000160, 8, 32}, {0X32000000000170, 8, 32},
295 : {0X32000000000180, 8, 32}, {0X32000000000190, 8, 32}, {0X320000000001a0, 8, 32},
296 : {0X320000000001b0, 8, 32}, {0X320000000001c0, 8, 32}, {0X320000000001d0, 8, 32},
297 : {0X320000000001e0, 8, 32}, {0X320000000001f0, 8, 32}, {0X32000000000200, 1, 32},
298 : {0X32000000000202, 1, 32}, {0X32000000000204, 1, 32}, {0X32000000000206, 1, 32},
299 : {0X32000000000208, 1, 32}, {0X3200000000020a, 1, 32}, {0X3200000000020c, 1, 32},
300 : {0X3200000000020e, 1, 32}, {0X32000000000400, 24, 32}, {0X32000000000440, 24, 32},
301 : {0X32000000000480, 24, 32}, {0X320000000004c0, 24, 32}, {0X32000000000600, 4, 32},
302 : {0X32000000000800, 4, 32}, {0X32000000000804, 4, 8}, {0X32000000000a00, 64, 8},
303 : {0X32000000000c00, 8, 16}, {0X32000000000e00, 8, 8}, {0X32000000001000, 4, 8},
304 : {0X32000000001200, 1, 16}, {0X32000000001400, 1, 8}, {0X32000000001600, 1, 8},
305 : {0X32000000001800, 1, 8}, {0X32000000001a00, 1, 32}, {0X32000000001c00, 1, 8},
306 : {0X32000000001e00, 1, 8}, {0X32000000002000, 64, 8}, {0X32000000002200, 4, 8},
307 : {0X32000000002400, 9, 32}, {0X32000000002600, 5, 32}, {0X32000000002608, 5, 32},
308 : {0X32000000002800, 1, 32}, {0X32000000002804, 3, 32}, {0X32000000002808, 1, 32},
309 : {0X3200000000280c, 1, 32}, {0X32000000002a00, 2, 16}, {0X32000000002c00, 1, 8},
310 : {0X39000000000000, 5, 8}, {0X39000000004000, 64, 8}, {0X39000000008000, 0x80, 32},
311 : {0X3900000000c000, 0x80, 32}, {0X39000000010000, 0x80, 32}, {0X39000000014000, 0x80, 32},
312 : {0X39000000014080, 0x80, 32}, {0X39000000014100, 0x80, 32}, {0X39000000014180, 0x80, 32},
313 : {0X39000000014200, 0x80, 32}, {0X39000000014280, 0x80, 32}, {0X39000000014300, 0x80, 32},
314 : {0X39000000014380, 0x80, 32}, {0X39000000014400, 0x80, 32}, {0X39000000014480, 0x80, 32},
315 : {0X39000000014500, 0x80, 32}, {0X39000000014580, 0x80, 32}, {0X39000000014600, 0x80, 32},
316 : {0X39000000014680, 0x80, 32}, {0X39000000014700, 0x80, 32}, {0X39000000014780, 0x80, 32},
317 : {0X39000000014800, 0x80, 32}, {0X39000000014880, 0x80, 32}, {0X39000000014900, 0x80, 32},
318 : {0X39000000014980, 0x80, 32}, {0X39000000014a00, 0x80, 32}, {0X39000000014a80, 0x80, 32},
319 : {0X39000000014b00, 0x80, 32}, {0X39000000014b80, 0x80, 32}, {0X39000000014c00, 0x80, 32},
320 : {0X39000000014c80, 0x80, 32}, {0X39000000014d00, 0x80, 32}, {0X39000000014d80, 0x80, 32},
321 : {0X39000000014e00, 0x80, 32}, {0X39000000014e80, 0x80, 32}, {0X39000000014f00, 0x80, 32},
322 36 : {0X39000000014f80, 0x80, 32}, {0X39000000018000, 0x200, 8}, {0X3900000001c000, 64, 8}};
323 : }
324 :
325 12 : std::vector<RegisterTable> CloudBaseRegister::GenAIVDbgOthersAddr()
326 : {
327 : return {{0X80000000000000, 5, 8}, {0X90000000000000, 9, 8}, {0X90000000000040, 8, 8}, {0X90000000000080, 13, 8},
328 : {0X900000000000c0, 8, 8}, {0Xa0000000000000, 3, 8}, {0Xa0000000000100, 3, 8}, {0Xa0000000000200, 3, 8},
329 : {0Xa0000000001000, 1, 8}, {0Xa0000000001100, 1, 8}, {0Xa0000000001200, 1, 8}, {0Xa0000000002100, 2, 8},
330 : {0Xa0000000002200, 2, 8}, {0Xa0000000003000, 1, 8}, {0Xa0000000008100, 3, 8}, {0Xb0000000000000, 1, 8},
331 : {0Xb0000000000008, 1, 8}, {0Xb0000000000010, 1, 8}, {0Xb0000000000018, 1, 8}, {0Xb0000000000020, 1, 8},
332 : {0Xb0000000000040, 1, 8}, {0Xb0000000000080, 1, 8}, {0Xb00000000000c0, 1, 8}, {0Xb0000000000100, 1, 8},
333 : {0Xb0000000000140, 1, 8}, {0Xb0000000000180, 1, 8}, {0Xb00000000001c0, 1, 8}, {0Xb00000000001c8, 1, 8},
334 : {0Xb0000000000200, 1, 8}, {0Xb0000000000240, 1, 8}, {0Xb0000000000280, 1, 8}, {0Xb0000000000288, 1, 8},
335 : {0Xb0000000000290, 1, 8}, {0Xb00000000002c0, 1, 8}, {0Xb00000000002c8, 1, 8}, {0Xb0000000000300, 1, 8},
336 : {0Xb0000000000340, 1, 8}, {0Xd0000000000000, 1, 8}, {0Xd0000000000008, 1, 8}, {0Xd0000000000010, 1, 8},
337 : {0Xd0000000000018, 1, 8}, {0Xd0000000000020, 1, 8}, {0Xd0000000000028, 1, 8}, {0Xd0000000000030, 1, 8},
338 36 : {0Xd0000000000038, 1, 8}};
339 : }
340 :
341 12 : void CloudBaseRegister::GenAICOffsetAddr()
342 : {
343 : std::vector<RegisterTable> regAICOffsetTab = {
344 : {0X80, 30, 4}, {0X1000, 3, 4}, {0X11f0, 1, 4}, {0X1200, 2, 4}, {0X1210, 1, 4}, {0X1400, 5, 4},
345 : {0X1500, 4, 4}, {0X2000, 1, 4}, {0X2010, 1, 4}, {0X2020, 1, 4}, {0X2030, 2, 4}, {0X2400, 1, 4},
346 : {0X2410, 2, 4}, {0X2808, 1, 4}, {0X4000, 5, 4}, {0X4020, 9, 4}, {0X4050, 4, 4}, {0X4070, 2, 4},
347 : {0X40f0, 2, 4}, {0X4140, 1, 4}, {0X4200, 4, 4}, {0X4260, 4, 4}, {0X42a0, 6, 4}, {0X4700, 1, 4},
348 : {0X4720, 1, 4}, {0X4730, 2, 4}, {0X4750, 3, 4}, {0X4760, 1, 4}, {0X48a0, 3, 4}, {0X48b0, 1, 4},
349 : {0X4980, 1, 4}, {0X4990, 1, 4}, {0X4998, 1, 4}, {0X5000, 1, 4}, {0X5008, 2, 4}, {0X5020, 2, 4},
350 : {0X5030, 1, 4}, {0X5040, 2, 4}, {0X5050, 3, 4}, {0X5060, 1, 4}, {0X50f0, 1, 4}, {0X5100, 19, 4},
351 : {0X5200, 2, 4}, {0X5300, 3, 4}, {0X5310, 1, 4}, {0X5320, 8, 4}, {0X53a0, 4, 4}, {0X5600, 3, 4},
352 : {0X5700, 1, 4}, {0X5720, 1, 4}, {0X5730, 4, 4}, {0X5900, 1, 4}, {0X5910, 1, 4}, {0X5920, 2, 4},
353 : {0X5930, 2, 4}, {0X5a00, 3, 4}, {0X5a80, 2, 4}, {0X6000, 2, 4}, {0X6020, 6, 4}, {0X6600, 2, 4},
354 : {0X6700, 1, 4}, {0X6708, 1, 4}, {0X6710, 1, 4}, {0X6718, 5, 4}, {0X673c, 1, 4}, {0X6900, 3, 4},
355 : {0X6910, 3, 4}, {0X6a00, 4, 4}, {0X6a18, 1, 4}, {0X6b04, 1, 4}, {0X6b0c, 3, 4}, {0X8000, 11, 4},
356 : {0X8030, 6, 4}, {0X8050, 9, 4}, {0X8080, 1, 4}, {0X8088, 6, 4}, {0X8100, 2, 4}, {0X8200, 3, 4},
357 : {0X8218, 1, 4}, {0X8230, 4, 4}, {0X8700, 2, 4}, {0X8720, 2, 4}, {0X8730, 2, 4}, {0X8900, 1, 4},
358 : {0X8920, 1, 4}, {0X8930, 2, 4}, {0X8940, 1, 4}, {0X9000, 4, 4}, {0X9014, 14, 4}, {0X9050, 4, 4},
359 : {0X9090, 3, 4}, {0X9200, 7, 4}, {0X9220, 11, 4}, {0X9300, 7, 4}, {0X9320, 4, 4}, {0X9500, 1, 4},
360 : {0X9600, 1, 4}, {0Xa000, 3, 4}, {0Xa020, 2, 4}, {0Xa600, 2, 4}, {0Xa700, 2, 4}, {0Xa710, 4, 4},
361 : {0Xa900, 1, 4}, {0Xa908, 1, 4}, {0Xa910, 1, 4}, {0Xaa00, 1, 4}, {0Xb000, 14, 4}, {0Xb070, 2, 4},
362 : {0Xb080, 14, 4},
363 24 : };
364 12 : registerTableMap_[RegisterType::AIC] = regAICOffsetTab;
365 12 : }
366 :
367 12 : void CloudBaseRegister::GenAIVOffsetAddr()
368 : {
369 : std::vector<RegisterTable> regAIVOffsetTab = {
370 : {0X80, 30, 4}, {0X1000, 3, 4}, {0X11f0, 1, 4}, {0X1500, 4, 4}, {0X2000, 1, 4}, {0X2010, 1, 4},
371 : {0X1200, 2, 4}, {0X1210, 1, 4}, {0X1400, 5, 4}, {0X2020, 1, 4}, {0X2030, 2, 4}, {0X2400, 1, 4},
372 : {0X4020, 9, 4}, {0X4050, 4, 4}, {0X4070, 2, 4}, {0X2410, 2, 4}, {0X2808, 1, 4}, {0X4000, 5, 4},
373 : {0X40f0, 2, 4}, {0X4140, 1, 4}, {0X4200, 4, 4}, {0X4260, 4, 4}, {0X42a0, 6, 4}, {0X4700, 1, 4},
374 : {0X4760, 1, 4}, {0X48a0, 3, 4}, {0X48b0, 1, 4}, {0X4720, 1, 4}, {0X4730, 2, 4}, {0X4750, 3, 4},
375 : {0X4980, 1, 4}, {0X4990, 1, 4}, {0X4998, 1, 4}, {0X5000, 1, 4}, {0X5008, 2, 4}, {0X5020, 2, 4},
376 : {0X5030, 1, 4}, {0X5040, 2, 4}, {0X5050, 3, 4}, {0X5060, 1, 4}, {0X50f0, 1, 4}, {0X5100, 19, 4},
377 : {0X5200, 2, 4}, {0X5300, 3, 4}, {0X5310, 1, 4}, {0X5320, 8, 4}, {0X53a0, 4, 4}, {0X5600, 3, 4},
378 : {0X5700, 1, 4}, {0X5720, 1, 4}, {0X5730, 4, 4}, {0X5900, 1, 4}, {0X5910, 1, 4}, {0X5920, 2, 4},
379 : {0X5930, 2, 4}, {0X5a00, 3, 4}, {0X5a80, 2, 4}, {0X6000, 2, 4}, {0X6020, 6, 4}, {0X6600, 2, 4},
380 : {0X6700, 1, 4}, {0X6708, 1, 4}, {0X6710, 1, 4}, {0X6718, 5, 4}, {0X673c, 1, 4}, {0X6900, 3, 4},
381 : {0X6910, 3, 4}, {0X6a00, 4, 4}, {0X6a18, 1, 4}, {0X6b04, 1, 4}, {0X6b0c, 3, 4}, {0X7004, 6, 4},
382 : {0X7030, 1, 4}, {0X7040, 3, 4}, {0X7080, 3, 4}, {0X70c0, 2, 4}, {0X7100, 6, 4}, {0X7200, 7, 4},
383 : {0X7700, 1, 4}, {0X7708, 1, 4}, {0X7720, 1, 4}, {0X7728, 1, 4}, {0X7730, 6, 4}, {0X7900, 1, 4},
384 : {0X7920, 1, 4}, {0X9000, 4, 4}, {0X9014, 14, 4}, {0X9050, 4, 4}, {0X9090, 3, 4}, {0X9200, 7, 4},
385 : {0X9220, 11, 4}, {0X9300, 7, 4}, {0X9320, 4, 4}, {0X9500, 1, 4}, {0X9600, 1, 4}, {0Xb000, 14, 4},
386 : {0Xb070, 2, 4}, {0Xb080, 14, 4},
387 24 : };
388 12 : registerTableMap_[RegisterType::AIV] = regAIVOffsetTab;
389 12 : }
390 :
391 0 : uint64_t CloudBaseRegister::GetAddr(uint64_t type, uint64_t regAddrHigh, uint64_t regAddrLow) const
392 : {
393 0 : return (type << MOUDLE_TYPE_SHIFT) | (regAddrHigh << HIGH_ADDR_SHIFT) | regAddrLow;
394 : }
395 :
396 0 : void CloudBaseRegister::GenAddrByStep(RegisterType regType, const std::vector<RegisterStepTable>& regStepTab)
397 : {
398 0 : for (const auto& stepTable : regStepTab) {
399 0 : uint64_t curStartAddr = stepTable.startAddr;
400 0 : for (uint32_t i = 0; i < stepTable.num; i++) {
401 0 : registerTableMap_[regType].emplace_back(curStartAddr, 1, stepTable.byteWidth);
402 0 : curStartAddr += stepTable.step;
403 : }
404 : }
405 0 : }
406 :
407 37 : void RegisterManager::CreateRegister()
408 : {
409 37 : auto* plat = CoredumpManager::Get();
410 37 : if (plat == nullptr) {
411 20 : return;
412 : }
413 17 : register_ = plat->CreateRegister();
414 : }
415 :
416 23 : RegisterManager::RegisterManager() { CreateRegister(); }
417 :
418 86 : RegisterManager& RegisterManager::GetInstance()
419 : {
420 86 : static RegisterManager instance;
421 86 : return instance;
422 : }
423 :
424 108 : const std::shared_ptr<RegisterInterface> RegisterManager::GetRegister() { return register_; }
425 : } // namespace Adx
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