Line data Source code
1 : /**
2 : * Copyright (c) 2025 Huawei Technologies Co., Ltd.
3 : * This program is free software, you can redistribute it and/or modify it under the terms and conditions of
4 : * CANN Open Software License Agreement Version 2.0 (the "License").
5 : * Please refer to the License for details. You may not use this file except in compliance with the License.
6 : * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR IMPLIED,
7 : * INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY, OR FITNESS FOR A PARTICULAR PURPOSE.
8 : * See LICENSE in the root of the software repository for the full text of the License.
9 : */
10 :
11 : #include "runtime/base.h"
12 : #include "dump_common.h"
13 : #include "register_config.h"
14 : #include "acc_error_info.h"
15 : #include "adump_platform_manager.h"
16 :
17 : namespace Adx {
18 :
19 177 : const std::vector<RegisterTable>& RegisterInterface::GetRegisterTable(RegisterType type) const
20 : {
21 177 : static std::vector<RegisterTable> defaultTables = {};
22 177 : return registerTableMap_.find(type) != registerTableMap_.end() ? registerTableMap_.at(type) : defaultTables;
23 : }
24 :
25 85 : const std::vector<RegisterType>& RegisterInterface::GetRegisterTypes(uint8_t coreType) const
26 : {
27 85 : static std::vector<RegisterType> defaultTypes = {};
28 85 : return registerTypeMap_.find(coreType) != registerTypeMap_.end() ? registerTypeMap_.at(coreType) : defaultTypes;
29 : }
30 :
31 85 : const std::vector<ErrorRegisterTable>& RegisterInterface::GetErrorRegisterTable() const
32 : {
33 85 : return ErrorRegisterMap_;
34 : }
35 :
36 10 : CloudV2Register::CloudV2Register()
37 : {
38 50 : registerTableMap_ = {
39 0 : {RegisterType::SU,
40 : {{GetAddr(0, 0), 32, 8}, // GPR0 - GPR31
41 : {GetAddr(0, 64), 1, 8}, // PC
42 : {GetAddr(0, 66), 8, 8}, // 66-73
43 : {GetAddr(0, 75), 4, 8}, // 75-78
44 : {GetAddr(0, 128), 12, 8}}}, // 128-139
45 0 : {RegisterType::VEC,
46 : {{GetAddr(256, 0), 2, 16}, // MASK CMPMASK
47 : {GetAddr(256, 2), 14, 8}, // 2-15
48 : {GetAddr(257, 0), 8, 16}}}, // VARF0 - VARF7
49 0 : {RegisterType::MTE,
50 : {{GetAddr(515, 0), 17, 8}, // 0-16
51 : {GetAddr(515, 23), 25, 8}}}, // AIPP_SPR_0 - AIPP_SPR_24
52 0 : {RegisterType::CUBE,
53 : {{GetAddr(768, 0), 1, 8}, // LOW_PRE_TBL
54 : {GetAddr(768, 0x2000), 1, 8}, // SMASK_INDEX
55 : {GetAddr(768, 0x4000), 1, 8}}}, // FIXP_PRE_BUF
56 110 : };
57 30 : registerTypeMap_ = {
58 : {CORE_TYPE_AIC, {RegisterType::SU, RegisterType::MTE, RegisterType::CUBE, RegisterType::BIU}},
59 50 : {CORE_TYPE_AIV, {RegisterType::SU, RegisterType::VEC, RegisterType::BIU}}};
60 200 : ErrorRegisterMap_ = {
61 : {RT_V100_AIC_ERR_0, 0x00000700, 4, "AIC_ERROR_0"}, {RT_V100_AIC_ERR_1, 0x00000704, 4, "AIC_ERROR_1"},
62 : {RT_V100_AIC_ERR_2, 0x00000760, 4, "AIC_ERROR_2"}, {RT_V100_AIC_ERR_3, 0x00000764, 4, "AIC_ERROR_3"},
63 : {RT_V100_AIC_ERR_4, 0x00000780, 4, "AIC_ERROR_4"}, {RT_V100_AIC_ERR_5, 0x00000790, 4, "AIC_ERROR_5"},
64 : {RT_V100_BIU_ERR_0, 0x00000710, 4, "BIU_ERR_INFO_0"}, {RT_V100_BIU_ERR_1, 0x00000714, 4, "BIU_ERR_INFO_1"},
65 : {RT_V100_CCU_ERR_0, 0x00000718, 4, "CCU_ERR_INFO_0"}, {RT_V100_CCU_ERR_1, 0x0000071C, 4, "CCU_ERR_INFO_1"},
66 : {RT_V100_IFU_ERR_0, 0x00000728, 4, "IFU_ERR_INFO_0"}, {RT_V100_IFU_ERR_1, 0x0000072C, 4, "IFU_ERR_INFO_1"},
67 : {RT_V100_MTE_ERR_0, 0x00000730, 4, "MTE_ERR_INFO_0"}, {RT_V100_MTE_ERR_1, 0x00000734, 4, "MTE_ERR_INFO_1"},
68 : {RT_V100_VEC_ERR_0, 0x00000738, 4, "VEC_ERR_INFO_0"}, {RT_V100_VEC_ERR_1, 0x0000073C, 4, "VEC_ERR_INFO_1"},
69 : {RT_V100_FIXP_ERR_0, 0x0000078C, 4, "FIXP_ERR_INFO_0"}, {RT_V100_FIXP_ERR_1, 0x000007C8, 4, "FIXP_ERR_INFO_1"},
70 : {RT_V100_CUBE_ERR_0, 0x00000720, 4, "CUBE_ERR_INFO"},
71 220 : };
72 100 : }
73 :
74 130 : uint64_t CloudV2Register::GetAddr(uint64_t regAddrHigh, uint64_t regAddrLow) const
75 : {
76 130 : return (regAddrHigh << HIGH_ADDR_SHIFT) | regAddrLow;
77 : }
78 :
79 11 : CloudV4Register::CloudV4Register()
80 : {
81 11 : GenAICDbgAddr();
82 11 : GenAIVDbgAddr();
83 11 : GenAICOffsetAddr();
84 11 : GenAIVOffsetAddr();
85 33 : registerTypeMap_ = {
86 : {CORE_TYPE_AIC, {RegisterType::AIC, RegisterType::AIC_DBG}},
87 : {CORE_TYPE_AIV, {RegisterType::AIV, RegisterType::AIV_DBG}}
88 55 : };
89 11 : InitErrorRegisterMap();
90 44 : }
91 :
92 11 : void CloudV4Register::InitErrorRegisterMap()
93 : {
94 363 : ErrorRegisterMap_ = {
95 : {RT_V200_SC_ERROR_T0_0, 0x4700, 4, "SC_ERROR_T0_0"},
96 : {RT_V200_SC_ERR_INFO_T0_0, 0x4730, 4, "SC_ERR_INFO_T0_0"},
97 : {RT_V200_SC_ERR_INFO_T0_1, 0x4734, 4, "SC_ERR_INFO_T0_1"},
98 : {RT_V200_SU_ERROR_T0_0, 0x5700, 4, "SU_ERROR_T0_0"},
99 : {RT_V200_SU_ERR_INFO_T0_0, 0x5730, 4, "SU_ERR_INFO_T0_0"},
100 : {RT_V200_SU_ERR_INFO_T0_1, 0x5734, 4, "SU_ERR_INFO_T0_1"},
101 : {RT_V200_SU_ERR_INFO_T0_2, 0x5738, 4, "SU_ERR_INFO_T0_2"},
102 : {RT_V200_SU_ERR_INFO_T0_3, 0x573C, 4, "SU_ERR_INFO_T0_3"},
103 : {RT_V200_MTE_ERROR_T0_0, 0x6700, 4, "MTE_ERROR_T0_0"},
104 : {RT_V200_MTE_ERROR_T1_0, 0x6708, 4, "MTE_ERROR_T1_0"},
105 : {RT_V200_MTE_ERR_INFO_T0_0, 0x6718, 4, "MTE_ERR_INFO_T0_0"},
106 : {RT_V200_MTE_ERR_INFO_T0_1, 0x671C, 4, "MTE_ERR_INFO_T0_1"},
107 : {RT_V200_MTE_ERR_INFO_T0_2, 0x6720, 4, "MTE_ERR_INFO_T0_2"},
108 : {RT_V200_MTE_ERR_INFO_T1_0, 0x6724, 4, "MTE_ERR_INFO_T1_0"},
109 : {RT_V200_MTE_ERR_INFO_T1_1, 0x6728, 4, "MTE_ERR_INFO_T1_1"},
110 : {RT_V200_MTE_ERR_INFO_T1_2, 0x673C, 4, "MTE_ERR_INFO_T1_2"},
111 : {RT_V200_VEC_ERROR_T0_0, 0x7700, 4, "VEC_ERROR_T0_0"},
112 : {RT_V200_VEC_ERROR_T0_2, 0x7708, 4, "VEC_ERROR_T0_2"},
113 : {RT_V200_VEC_ERR_INFO_T0_0, 0x7730, 4, "VEC_ERR_INFO_T0_0"},
114 : {RT_V200_VEC_ERR_INFO_T0_1, 0x7734, 4, "VEC_ERR_INFO_T0_1"},
115 : {RT_V200_VEC_ERR_INFO_T0_2, 0x7738, 4, "VEC_ERR_INFO_T0_2"},
116 : {RT_V200_VEC_ERR_INFO_T0_3, 0x773C, 4, "VEC_ERR_INFO_T0_3"},
117 : {RT_V200_VEC_ERR_INFO_T0_4, 0x7740, 4, "VEC_ERR_INFO_T0_4"},
118 : {RT_V200_VEC_ERR_INFO_T0_5, 0x7744, 4, "VEC_ERR_INFO_T0_5"},
119 : {RT_V200_CUBE_ERROR_T0_0, 0x8700, 4, "CUBE_ERROR_T0_0"},
120 : {RT_V200_CUBE_ERROR_T0_1, 0x8704, 4, "CUBE_ERROR_T0_1"},
121 : {RT_V200_CUBE_ERR_INFO_T0_0, 0x8730, 4, "CUBE_ERR_INFO_T0_0"},
122 : {RT_V200_CUBE_ERR_INFO_T0_1, 0x8734, 4, "CUBE_ERR_INFO_T0_1"},
123 : {RT_V200_L1_ERROR_T0_0, 0xA700, 4, "L1_ERROR_T0_0"},
124 : {RT_V200_L1_ERROR_T0_1, 0xA704, 4, "L1_ERROR_T0_1"},
125 : {RT_V200_L1_ERR_INFO_T0_0, 0xA718, 4, "L1_ERR_INFO_T0_0"},
126 : {RT_V200_L1_ERR_INFO_T0_1, 0xA71C, 4, "L1_ERR_INFO_T0_1"},
127 385 : };
128 33 : }
129 :
130 11 : void CloudV4Register::GenAICDbgAddr(){
131 : std::vector<RegisterTable> regAICDbgTab = {
132 : // SU(for AIC)
133 : {0X10000000000000,32, 8}, {0X10000000000040, 15, 8}, {0X10000000000080, 12, 8},
134 : {0X15000000000000, 32, 8}, {0X15800000000000, 32, 8}, {0X16000000000000, 16, 8},
135 : {0X16800000000000, 32, 8},
136 : // MTE(for AIC)
137 : {0X21000000000000, 1, 8}, {0X22000000000000, 2, 8}, {0X22000000000003, 4, 8},
138 : {0X22000000000012, 1, 8}, {0X24000000000014, 1, 8},
139 : // CUBE
140 : {0X40000000000000, 8, 8}, {0X40000000000008, 8, 8}, {0X40000000000010, 8, 8},
141 : {0X40000000000018, 8, 8}, {0X40000000000020, 8, 8}, {0X40000000000028, 8, 8},
142 : {0X40000000000030, 8, 8}, {0X40000000000038, 8, 8}, {0X40000000000040, 8, 8},
143 : {0X40000000000048, 8, 8}, {0X40000000000050, 8, 8}, {0X40000000000058, 8, 8},
144 : {0X40000000000060, 8, 8},
145 : // L1
146 : {0X60000000000000, 10, 8}, {0X61000000000000, 11, 8}, {0X67000000000000, 1, 8},
147 : // others
148 : {0X80000000000000, 5, 8}, {0X90000000000000, 9, 8}, {0X90000000000040, 8, 8},
149 : {0X90000000000080, 13, 8}, {0X900000000000c0, 8, 8}, {0Xa0000000000000, 3, 8},
150 : {0Xa0000000000100, 3, 8}, {0Xa0000000000200, 3, 8}, {0Xa0000000001000, 1, 8},
151 : {0Xa0000000001100, 1, 8}, {0Xa0000000001200, 1, 8}, {0Xa0000000002100, 2, 8},
152 : {0Xa0000000002200, 2, 8}, {0Xa0000000003000, 1, 8}, {0Xa0000000008100, 3, 8},
153 : {0Xc0000000000000, 16, 8}, {0Xd0000000000000, 1, 8}, {0Xd0000000000008, 1, 8},
154 : {0Xd0000000000010, 1, 8}, {0Xd0000000000018, 1, 8}, {0Xd0000000000020, 1, 8},
155 : {0Xd0000000000028, 1, 8}, {0Xd0000000000030, 1, 8}, {0Xd0000000000038, 1, 8},
156 : {0Xe0000000000000, 5, 8}, {0Xe0000000000100, 3, 8}, {0Xe0000000000200, 6, 8},
157 : {0Xe0000000000300, 2, 8}, {0Xe0000000000400, 1, 8}, {0Xe0000000000500, 9, 8},
158 : {0Xe0000000000600, 16, 8},
159 22 : };
160 11 : registerTableMap_[RegisterType::AIC_DBG] = regAICDbgTab;
161 11 : }
162 :
163 11 : void CloudV4Register::GenAIVDbgAddr()
164 : {
165 11 : std::vector<RegisterTable> regAIVDbgTab;
166 11 : auto suTab = GenAIVDbgSUAddr();
167 11 : auto mteTab = GenAIVDbgMTEAddr();
168 11 : auto vecRbTab = GenAIVDbgVECRBAddr();
169 11 : auto othersTab = GenAIVDbgOthersAddr();
170 11 : regAIVDbgTab.insert(regAIVDbgTab.end(), suTab.begin(), suTab.end());
171 11 : regAIVDbgTab.insert(regAIVDbgTab.end(), mteTab.begin(), mteTab.end());
172 11 : regAIVDbgTab.insert(regAIVDbgTab.end(), vecRbTab.begin(), vecRbTab.end());
173 11 : regAIVDbgTab.insert(regAIVDbgTab.end(), othersTab.begin(), othersTab.end());
174 11 : registerTableMap_[RegisterType::AIV_DBG] = regAIVDbgTab;
175 11 : }
176 :
177 11 : std::vector<RegisterTable> CloudV4Register::GenAIVDbgSUAddr()
178 : {
179 : return {
180 : {0X10000000000000, 32, 8}, {0X10000000000040, 15, 8}, {0X10000000000080, 12, 8},
181 : {0X15000000000000, 32, 8}, {0X15800000000000, 32, 8}, {0X16000000000000, 16, 8},
182 : {0X16800000000000, 16, 8},
183 33 : };
184 : }
185 :
186 11 : std::vector<RegisterTable> CloudV4Register::GenAIVDbgMTEAddr()
187 : {
188 : return {
189 : {0X21000000000000, 1, 8}, {0X22000000000002, 1, 8}, {0X22000000000007, 3, 8},
190 : {0X2200000000000d, 3, 8}, {0X22000000000016, 9, 8}
191 33 : };
192 : }
193 :
194 11 : std::vector<RegisterTable> CloudV4Register::GenAIVDbgVECRBAddr()
195 : {
196 : return {
197 : {0X32000000000000, 8, 32}, {0X32000000000010, 8, 32}, {0X32000000000020, 8, 32},
198 : {0X32000000000030, 8, 32}, {0X32000000000040, 8, 32}, {0X32000000000050, 8, 32},
199 : {0X32000000000060, 8, 32}, {0X32000000000070, 8, 32}, {0X32000000000080, 8, 32},
200 : {0X32000000000090, 8, 32}, {0X320000000000a0, 8, 32}, {0X320000000000b0, 8, 32},
201 : {0X320000000000c0, 8, 32}, {0X320000000000d0, 8, 32}, {0X320000000000e0, 8, 32},
202 : {0X320000000000f0, 8, 32}, {0X32000000000100, 8, 32}, {0X32000000000110, 8, 32},
203 : {0X32000000000120, 8, 32}, {0X32000000000130, 8, 32}, {0X32000000000140, 8, 32},
204 : {0X32000000000150, 8, 32}, {0X32000000000160, 8, 32}, {0X32000000000170, 8, 32},
205 : {0X32000000000180, 8, 32}, {0X32000000000190, 8, 32}, {0X320000000001a0, 8, 32},
206 : {0X320000000001b0, 8, 32}, {0X320000000001c0, 8, 32}, {0X320000000001d0, 8, 32},
207 : {0X320000000001e0, 8, 32}, {0X320000000001f0, 8, 32}, {0X32000000000200, 1, 32},
208 : {0X32000000000202, 1, 32}, {0X32000000000204, 1, 32}, {0X32000000000206, 1, 32},
209 : {0X32000000000208, 1, 32}, {0X3200000000020a, 1, 32}, {0X3200000000020c, 1, 32},
210 : {0X3200000000020e, 1, 32}, {0X32000000000400, 24, 32}, {0X32000000000440, 24, 32},
211 : {0X32000000000480, 24, 32}, {0X320000000004c0, 24, 32}, {0X32000000000600, 4, 32},
212 : {0X32000000000800, 4, 32}, {0X32000000000804, 4, 8}, {0X32000000000a00, 64, 8},
213 : {0X32000000000c00, 8, 16}, {0X32000000000e00, 8, 8}, {0X32000000001000, 4, 8},
214 : {0X32000000001200, 1, 16}, {0X32000000001400, 1, 8}, {0X32000000001600, 1, 8},
215 : {0X32000000001800, 1, 8}, {0X32000000001a00, 1, 32}, {0X32000000001c00, 1, 8},
216 : {0X32000000001e00, 1, 8}, {0X32000000002000, 64, 8}, {0X32000000002200, 4, 8},
217 : {0X32000000002400, 9, 32}, {0X32000000002600, 5, 32}, {0X32000000002608, 5, 32},
218 : {0X32000000002800, 1, 32}, {0X32000000002804, 3, 32}, {0X32000000002808, 1, 32},
219 : {0X3200000000280c, 1, 32}, {0X32000000002a00, 2, 16}, {0X32000000002c00, 1, 8},
220 : {0X39000000000000, 5, 8}, {0X39000000004000, 64, 8}, {0X39000000008000, 0x80, 32},
221 : {0X3900000000c000, 0x80, 32}, {0X39000000010000, 0x80, 32},
222 : {0X39000000014000, 0x80, 32}, {0X39000000014080, 0x80, 32},
223 : {0X39000000014100, 0x80, 32}, {0X39000000014180, 0x80, 32},
224 : {0X39000000014200, 0x80, 32}, {0X39000000014280, 0x80, 32},
225 : {0X39000000014300, 0x80, 32}, {0X39000000014380, 0x80, 32},
226 : {0X39000000014400, 0x80, 32}, {0X39000000014480, 0x80, 32},
227 : {0X39000000014500, 0x80, 32}, {0X39000000014580, 0x80, 32},
228 : {0X39000000014600, 0x80, 32}, {0X39000000014680, 0x80, 32},
229 : {0X39000000014700, 0x80, 32}, {0X39000000014780, 0x80, 32},
230 : {0X39000000014800, 0x80, 32}, {0X39000000014880, 0x80, 32},
231 : {0X39000000014900, 0x80, 32}, {0X39000000014980, 0x80, 32},
232 : {0X39000000014a00, 0x80, 32}, {0X39000000014a80, 0x80, 32},
233 : {0X39000000014b00, 0x80, 32}, {0X39000000014b80, 0x80, 32},
234 : {0X39000000014c00, 0x80, 32}, {0X39000000014c80, 0x80, 32},
235 : {0X39000000014d00, 0x80, 32}, {0X39000000014d80, 0x80, 32},
236 : {0X39000000014e00, 0x80, 32}, {0X39000000014e80, 0x80, 32},
237 : {0X39000000014f00, 0x80, 32}, {0X39000000014f80, 0x80, 32},
238 : {0X39000000018000, 0x200, 8}, {0X3900000001c000, 64, 8}
239 33 : };
240 : }
241 :
242 11 : std::vector<RegisterTable> CloudV4Register::GenAIVDbgOthersAddr()
243 : {
244 : return {
245 : {0X80000000000000, 5, 8}, {0X90000000000000, 9, 8}, {0X90000000000040, 8, 8},
246 : {0X90000000000080, 13, 8}, {0X900000000000c0, 8, 8}, {0Xa0000000000000, 3, 8},
247 : {0Xa0000000000100, 3, 8}, {0Xa0000000000200, 3, 8}, {0Xa0000000001000, 1, 8},
248 : {0Xa0000000001100, 1, 8}, {0Xa0000000001200, 1, 8}, {0Xa0000000002100, 2, 8},
249 : {0Xa0000000002200, 2, 8}, {0Xa0000000003000, 1, 8}, {0Xa0000000008100, 3, 8},
250 : {0Xb0000000000000, 1, 8}, {0Xb0000000000008, 1, 8}, {0Xb0000000000010, 1, 8},
251 : {0Xb0000000000018, 1, 8}, {0Xb0000000000020, 1, 8}, {0Xb0000000000040, 1, 8},
252 : {0Xb0000000000080, 1, 8}, {0Xb00000000000c0, 1, 8}, {0Xb0000000000100, 1, 8},
253 : {0Xb0000000000140, 1, 8}, {0Xb0000000000180, 1, 8}, {0Xb00000000001c0, 1, 8},
254 : {0Xb00000000001c8, 1, 8}, {0Xb0000000000200, 1, 8}, {0Xb0000000000240, 1, 8},
255 : {0Xb0000000000280, 1, 8}, {0Xb0000000000288, 1, 8}, {0Xb0000000000290, 1, 8},
256 : {0Xb00000000002c0, 1, 8}, {0Xb00000000002c8, 1, 8}, {0Xb0000000000300, 1, 8},
257 : {0Xb0000000000340, 1, 8}, {0Xd0000000000000, 1, 8}, {0Xd0000000000008, 1, 8},
258 : {0Xd0000000000010, 1, 8}, {0Xd0000000000018, 1, 8}, {0Xd0000000000020, 1, 8},
259 : {0Xd0000000000028, 1, 8}, {0Xd0000000000030, 1, 8}, {0Xd0000000000038, 1, 8}
260 33 : };
261 : }
262 :
263 11 : void CloudV4Register::GenAICOffsetAddr(){
264 : std::vector<RegisterTable> regAICOffsetTab = {
265 : {0X80,30, 4}, {0X1000, 3, 4}, {0X11f0, 1, 4},
266 : {0X1200, 2, 4}, {0X1210, 1, 4}, {0X1400, 5, 4},
267 : {0X1500, 4, 4}, {0X2000, 1, 4}, {0X2010, 1, 4},
268 : {0X2020, 1, 4}, {0X2030, 2, 4}, {0X2400, 1, 4},
269 : {0X2410, 2, 4}, {0X2808, 1, 4}, {0X4000, 5, 4},
270 : {0X4020, 9, 4}, {0X4050, 4, 4}, {0X4070, 2, 4},
271 : {0X40f0, 2, 4}, {0X4140, 1, 4}, {0X4200, 4, 4},
272 : {0X4260, 4, 4}, {0X42a0, 6, 4}, {0X4700, 1, 4},
273 : {0X4720, 1, 4}, {0X4730, 2, 4}, {0X4750, 3, 4},
274 : {0X4760, 1, 4}, {0X48a0, 3, 4}, {0X48b0, 1, 4},
275 : {0X4980, 1, 4}, {0X4990, 1, 4}, {0X4998, 1, 4},
276 : {0X5000, 1, 4}, {0X5008, 2, 4}, {0X5020, 2, 4},
277 : {0X5030, 1, 4}, {0X5040, 2, 4}, {0X5050, 3, 4},
278 : {0X5060, 1, 4}, {0X50f0, 1, 4}, {0X5100, 19, 4},
279 : {0X5200, 2, 4}, {0X5300, 3, 4}, {0X5310, 1, 4},
280 : {0X5320, 8, 4}, {0X53a0, 4, 4}, {0X5600, 3, 4},
281 : {0X5700, 1, 4}, {0X5720, 1, 4}, {0X5730, 4, 4},
282 : {0X5900, 1, 4}, {0X5910, 1, 4}, {0X5920, 2, 4},
283 : {0X5930, 2, 4}, {0X5a00, 3, 4}, {0X5a80, 2, 4},
284 : {0X6000, 2, 4}, {0X6020, 6, 4}, {0X6600, 2, 4},
285 : {0X6700, 1, 4}, {0X6708, 1, 4}, {0X6710, 1, 4},
286 : {0X6718, 5, 4}, {0X673c, 1, 4}, {0X6900, 3, 4},
287 : {0X6910, 3, 4}, {0X6a00, 4, 4}, {0X6a18, 1, 4},
288 : {0X6b04, 1, 4}, {0X6b0c, 3, 4},
289 : {0X8000, 11, 4}, {0X8030, 6, 4},
290 : {0X8050, 9, 4}, {0X8080, 1, 4},
291 : {0X8088, 6, 4}, {0X8100, 2, 4},
292 : {0X8200, 3, 4}, {0X8218, 1, 4},
293 : {0X8230, 4, 4}, {0X8700, 2, 4},
294 : {0X8720, 2, 4}, {0X8730, 2, 4},
295 : {0X8900, 1, 4}, {0X8920, 1, 4},
296 : {0X8930, 2, 4}, {0X8940, 1, 4},
297 : {0X9000, 4, 4}, {0X9014, 14, 4},
298 : {0X9050, 4, 4}, {0X9090, 3, 4},
299 : {0X9200, 7, 4}, {0X9220, 11, 4},
300 : {0X9300, 7, 4}, {0X9320, 4, 4},
301 : {0X9500, 1, 4}, {0X9600, 1, 4},
302 : {0Xa000, 3, 4}, {0Xa020, 2, 4},
303 : {0Xa600, 2, 4}, {0Xa700, 2, 4},
304 : {0Xa710, 4, 4}, {0Xa900, 1, 4},
305 : {0Xa908, 1, 4}, {0Xa910, 1, 4},
306 : {0Xaa00, 1, 4}, {0Xb000, 14, 4},
307 : {0Xb070, 2, 4}, {0Xb080, 14, 4},
308 22 : };
309 11 : registerTableMap_[RegisterType::AIC] = regAICOffsetTab;
310 11 : }
311 :
312 11 : void CloudV4Register::GenAIVOffsetAddr(){
313 : std::vector<RegisterTable> regAIVOffsetTab = {
314 : {0X80,30, 4}, {0X1000, 3, 4}, {0X11f0, 1, 4},
315 : {0X1500, 4, 4}, {0X2000, 1, 4}, {0X2010, 1, 4},
316 : {0X1200, 2, 4}, {0X1210, 1, 4}, {0X1400, 5, 4},
317 : {0X2020, 1, 4}, {0X2030, 2, 4}, {0X2400, 1, 4},
318 : {0X4020, 9, 4}, {0X4050, 4, 4}, {0X4070, 2, 4},
319 : {0X2410, 2, 4}, {0X2808, 1, 4}, {0X4000, 5, 4},
320 : {0X40f0, 2, 4}, {0X4140, 1, 4}, {0X4200, 4, 4},
321 : {0X4260, 4, 4}, {0X42a0, 6, 4}, {0X4700, 1, 4},
322 : {0X4760, 1, 4}, {0X48a0, 3, 4}, {0X48b0, 1, 4},
323 : {0X4720, 1, 4}, {0X4730, 2, 4}, {0X4750, 3, 4},
324 : {0X4980, 1, 4}, {0X4990, 1, 4}, {0X4998, 1, 4},
325 : {0X5000, 1, 4}, {0X5008, 2, 4}, {0X5020, 2, 4},
326 : {0X5030, 1, 4}, {0X5040, 2, 4}, {0X5050, 3, 4},
327 : {0X5060, 1, 4}, {0X50f0, 1, 4},
328 : {0X5100, 19, 4}, {0X5200, 2, 4},
329 : {0X5300, 3, 4}, {0X5310, 1, 4},
330 : {0X5320, 8, 4}, {0X53a0, 4, 4},
331 : {0X5600, 3, 4}, {0X5700, 1, 4},
332 : {0X5720, 1, 4}, {0X5730, 4, 4},
333 : {0X5900, 1, 4}, {0X5910, 1, 4},
334 : {0X5920, 2, 4}, {0X5930, 2, 4},
335 : {0X5a00, 3, 4}, {0X5a80, 2, 4},
336 : {0X6000, 2, 4}, {0X6020, 6, 4},
337 : {0X6600, 2, 4}, {0X6700, 1, 4},
338 : {0X6708, 1, 4}, {0X6710, 1, 4},
339 : {0X6718, 5, 4}, {0X673c, 1, 4},
340 : {0X6900, 3, 4}, {0X6910, 3, 4},
341 : {0X6a00, 4, 4}, {0X6a18, 1, 4},
342 : {0X6b04, 1, 4}, {0X6b0c, 3, 4},
343 : {0X7004, 6, 4}, {0X7030, 1, 4},
344 : {0X7040, 3, 4}, {0X7080, 3, 4},
345 : {0X70c0, 2, 4}, {0X7100, 6, 4},
346 : {0X7200, 7, 4}, {0X7700, 1, 4},
347 : {0X7708, 1, 4}, {0X7720, 1, 4},
348 : {0X7728, 1, 4}, {0X7730, 6, 4},
349 : {0X7900, 1, 4}, {0X7920, 1, 4},
350 : {0X9000, 4, 4}, {0X9014, 14, 4},
351 : {0X9050, 4, 4}, {0X9090, 3, 4},
352 : {0X9200, 7, 4}, {0X9220, 11, 4},
353 : {0X9300, 7, 4}, {0X9320, 4, 4},
354 : {0X9500, 1, 4}, {0X9600, 1, 4},
355 : {0Xb000, 14, 4}, {0Xb070, 2, 4},
356 : {0Xb080, 14, 4},
357 22 : };
358 11 : registerTableMap_[RegisterType::AIV] = regAIVOffsetTab;
359 11 : }
360 :
361 0 : uint64_t CloudV4Register::GetAddr(uint64_t type, uint64_t regAddrHigh, uint64_t regAddrLow) const
362 : {
363 0 : return (type << MOUDLE_TYPE_SHIFT) | (regAddrHigh << HIGH_ADDR_SHIFT) | regAddrLow;
364 : }
365 :
366 0 : void CloudV4Register::GenAddrByStep(RegisterType regType, const std::vector<RegisterStepTable>& regStepTab)
367 : {
368 0 : for (const auto& stepTable : regStepTab) {
369 0 : uint64_t curStartAddr = stepTable.startAddr;
370 0 : for (uint32_t i = 0; i < stepTable.num; i++) {
371 0 : registerTableMap_[regType].emplace_back(curStartAddr, 1, stepTable.byteWidth);
372 0 : curStartAddr += stepTable.step;
373 : }
374 : }
375 0 : }
376 :
377 35 : void RegisterManager::CreateRegister()
378 : {
379 35 : auto *plat = CoredumpManager::Get();
380 35 : if (plat == nullptr) {
381 20 : return;
382 : }
383 15 : register_ = plat->CreateRegister();
384 : }
385 :
386 22 : RegisterManager::RegisterManager()
387 : {
388 22 : CreateRegister();
389 22 : }
390 :
391 86 : RegisterManager &RegisterManager::GetInstance()
392 : {
393 86 : static RegisterManager instance;
394 86 : return instance;
395 : }
396 :
397 107 : const std::shared_ptr<RegisterInterface> RegisterManager::GetRegister()
398 : {
399 107 : return register_;
400 : }
401 : }
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