LCOV - code coverage report
Current view: top level - legacy/ascend950/service/collective/alg/coll_alg_factory/alg_ccu_context/reduce - ccu_instruction_reduce_nhr1d_mem2mem.h (source / functions) Coverage Total Hit
Test: coverage.info Lines: 0.0 % 66 0
Test Date: 2026-08-18 17:47:01 Functions: 0.0 % 9 0

            Line data    Source code
       1              : /**
       2              :  * Copyright (c) 2025 Huawei Technologies Co., Ltd.
       3              :  * This program is free software, you can redistribute it and/or modify it under the terms and conditions of
       4              :  * CANN Open Software License Agreement Version 2.0 (the "License").
       5              :  * Please refer to the License for details. You may not use this file except in compliance with the License.
       6              :  * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR IMPLIED,
       7              :  * INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY, OR FITNESS FOR A PARTICULAR PURPOSE.
       8              :  * See LICENSE in the root of the software repository for the full text of the License.
       9              :  */
      10              : 
      11              : #ifndef HCCLV2_CCU_INSTRUCTION_REDUCE_NHR_1D_H_
      12              : #define HCCLV2_CCU_INSTRUCTION_REDUCE_NHR_1D_H_
      13              : 
      14              : #include "template_utils.h"
      15              : #include "instruction.h"
      16              : #include "ins_queue.h"
      17              : #include "ccu_context_utils.h"
      18              : #include "ccu_ctx_signature.h"
      19              : #include "ccu_ins.h"
      20              : #include "ccu_rank_group.h"
      21              : #include "ccu_instruction_all_reduce_nhr1d_mem2mem.h"
      22              : 
      23              : namespace Hccl {
      24              : 
      25              : using NHRStepInfo = struct NHRStepInfoDef;
      26              : 
      27              : // 为ReduceNHR1D实现的CCUIns、CCUCtxArg与CCUTaskArg
      28              : class CcuCtxArgReduceNHR1D : public CcuCtxArg {
      29              : public:
      30            0 :     explicit CcuCtxArgReduceNHR1D(
      31              :         const std::vector<uint64_t>& dimSize, uint32_t rankId, uint32_t rootId, uint32_t axisId, uint32_t axisSize,
      32              :         const std::vector<NHRStepInfo> stepInfoVector, const std::map<u32, u32> indexMap, const CollAlgOperator& op,
      33              :         const std::vector<std::vector<RankId>>& tempVTopo)
      34            0 :         : dimSize_(dimSize),
      35            0 :           rankId_(rankId),
      36            0 :           rootId_(rootId),
      37            0 :           axisId_(axisId),
      38            0 :           axisSize_(axisSize),
      39            0 :           stepInfoVector_(stepInfoVector),
      40            0 :           indexMap_(indexMap),
      41            0 :           op_(op),
      42            0 :           tempVTopo_(tempVTopo)
      43            0 :     {}
      44            0 :     CcuCtxSignature GetCtxSignature() const override
      45              :     {
      46            0 :         CcuCtxSignature signature;
      47            0 :         GenerateCcuCtxSignature(signature, CcuInstType::CCU_REDUCE_NHR_1D_MEM2MEM, op_, tempVTopo_);
      48            0 :         return signature;
      49            0 :     }
      50              :     std::vector<uint64_t> dimSize_;
      51              :     uint32_t rankId_;
      52              :     uint32_t rootId_;
      53              :     uint32_t axisId_;
      54              :     uint32_t axisSize_;
      55              :     std::vector<NHRStepInfo> stepInfoVector_;
      56              :     std::map<u32, u32> indexMap_;
      57              :     CollAlgOperator op_;
      58              :     std::vector<std::vector<RankId>> tempVTopo_;
      59              : };
      60              : 
      61              : class CcuTaskArgReduceNHR1D : public CcuTaskArg {
      62              : public:
      63            0 :     explicit CcuTaskArgReduceNHR1D(
      64              :         uint64_t inputAddr, uint64_t outputAddr, uint64_t token, uint64_t isInputOutputEqual, uint64_t die0Size,
      65              :         uint64_t die1Size, uint64_t die0SliceSize, uint64_t die1SliceSize, uint64_t die0LastSliceSize,
      66              :         uint64_t die1LastSliceSize)
      67            0 :         : inputAddr_(inputAddr),
      68            0 :           outputAddr_(outputAddr),
      69            0 :           token_(token),
      70            0 :           isInputOutputEqual_(isInputOutputEqual),
      71            0 :           die0Size_(die0Size),
      72            0 :           die1Size_(die1Size),
      73            0 :           die0SliceSize_(die0SliceSize),
      74            0 :           die1SliceSize_(die1SliceSize),
      75            0 :           die0LastSliceSize_(die0LastSliceSize),
      76            0 :           die1LastSliceSize_(die1LastSliceSize)
      77            0 :     {}
      78              : 
      79              :     uint64_t inputAddr_;
      80              :     uint64_t outputAddr_;
      81              :     uint64_t token_;
      82              :     uint64_t isInputOutputEqual_;
      83              :     uint64_t die0Size_;
      84              :     uint64_t die1Size_;
      85              :     uint64_t die0SliceSize_;
      86              :     uint64_t die1SliceSize_;
      87              :     uint64_t die0LastSliceSize_;
      88              :     uint64_t die1LastSliceSize_;
      89              : };
      90              : 
      91              : class CcuInstructionReduceNHR1D : public CcuInstruction {
      92              : public:
      93            0 :     CcuInstructionReduceNHR1D() : CcuInstruction() {}
      94              : 
      95            0 :     void Init(
      96              :         uint32_t rankId, uint32_t rootId, uint64_t inputAddr, uint64_t outputAddr, uint32_t axisId, uint32_t axisSize,
      97              :         uint64_t die0Size, uint64_t die1Size, uint64_t die0SliceSize, uint64_t die1SliceSize,
      98              :         uint64_t die0LastSliceSize, uint64_t die1LastSliceSize, std::vector<NHRStepInfo> stepInfoVector,
      99              :         std::map<u32, u32> indexMap, uint64_t token, uint64_t isInputOutputEqual, CollAlgOperator& op,
     100              :         std::vector<std::vector<RankId>>& tempVTopo)
     101              :     {
     102            0 :         u32 maxDimNum = 1;
     103            0 :         if (tempVTopo.size() != maxDimNum) {
     104            0 :             THROW<InvalidParamsException>(
     105            0 :                 StringFormat("[CcuInstructionReduceNHR1D] tempVTopo size is not 1, size is [%zu].", tempVTopo.size()));
     106              :         }
     107            0 :         dimSize_.push_back(tempVTopo[0].size());
     108            0 :         rankId_ = rankId;
     109            0 :         rootId_ = rootId;
     110            0 :         inputAddr_ = inputAddr;
     111            0 :         outputAddr_ = outputAddr;
     112            0 :         axisId_ = axisId;
     113            0 :         axisSize_ = axisSize;
     114            0 :         die0Size_ = die0Size;
     115            0 :         die1Size_ = die1Size;
     116            0 :         die0SliceSize_ = die0SliceSize;
     117            0 :         die1SliceSize_ = die1SliceSize;
     118            0 :         die0LastSliceSize_ = die0LastSliceSize;
     119            0 :         die1LastSliceSize_ = die1LastSliceSize;
     120            0 :         stepInfoVector_ = stepInfoVector;
     121            0 :         indexMap_ = indexMap;
     122            0 :         token_ = token;
     123            0 :         isInputOutputEqual_ = isInputOutputEqual;
     124            0 :         op_ = op;
     125            0 :         tempVTopo_ = tempVTopo;
     126            0 :         return;
     127              :     }
     128              : 
     129            0 :     CcuInstType GetInstType() const override
     130              :     {
     131            0 :         HCCL_INFO("CcuInstructionReduceNHR1D instype is CCU_REDUCE_NHR_1D_MEM2MEM.");
     132            0 :         return instType_;
     133              :     }
     134              : 
     135            0 :     std::string Describe() const override
     136              :     {
     137              :         return StringFormat(
     138            0 :             "CcuInstructionReduceNHR1D rankId [%u], instType[%s]", rankId_, instType_.Describe().c_str());
     139              :     }
     140              : 
     141              :     void SetInstType(CcuInstType instType) { instType_ = instType; }
     142              : 
     143            0 :     std::unique_ptr<CcuCtxArg> GetCtxArg() const override
     144              :     {
     145            0 :         return std::make_unique<CcuCtxArgReduceNHR1D>(
     146            0 :             dimSize_, rankId_, rootId_, axisId_, axisSize_, stepInfoVector_, indexMap_, op_, tempVTopo_);
     147              :     }
     148              : 
     149            0 :     std::unique_ptr<CcuTaskArg> GetTaskArg() const override
     150              :     {
     151            0 :         return std::make_unique<CcuTaskArgReduceNHR1D>(
     152            0 :             inputAddr_, outputAddr_, token_, isInputOutputEqual_, die0Size_, die1Size_, die0SliceSize_, die1SliceSize_,
     153            0 :             die0LastSliceSize_, die1LastSliceSize_);
     154              :     }
     155              : 
     156              : private:
     157              :     CcuInstType instType_ = CcuInstType::CCU_REDUCE_NHR_1D_MEM2MEM;
     158              :     std::vector<uint64_t> dimSize_;
     159              :     uint32_t rankId_{0};
     160              :     uint32_t rootId_{0};
     161              :     uint32_t axisId_{0};
     162              :     uint32_t axisSize_{0};
     163              :     uint64_t inputAddr_{0};
     164              :     uint64_t outputAddr_{0};
     165              :     uint64_t die0Size_{0};
     166              :     uint64_t die1Size_{0};
     167              :     uint64_t die0SliceSize_{0};
     168              :     uint64_t die1SliceSize_{0};
     169              :     uint64_t die0LastSliceSize_{0};
     170              :     uint64_t die1LastSliceSize_{0};
     171              :     uint64_t isInputOutputEqual_{0};
     172              :     CollAlgOperator op_;
     173              :     std::vector<NHRStepInfo> stepInfoVector_;
     174              :     std::map<u32, u32> indexMap_;
     175              :     uint64_t token_{0};
     176              :     std::vector<std::vector<RankId>> tempVTopo_;
     177              : };
     178              : } // namespace Hccl
     179              : 
     180              : #endif // HCCLV2_CCU_INSTRUCTION_ALL_REDUCE_NHR_1D_H_
        

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