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1 : /**
2 : * Copyright (c) 2025 Huawei Technologies Co., Ltd.
3 : * This program is free software, you can redistribute it and/or modify it under the terms and conditions of
4 : * CANN Open Software License Agreement Version 2.0 (the "License").
5 : * Please refer to the License for details. You may not use this file except in compliance with the License.
6 : * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR IMPLIED,
7 : * INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY, OR FITNESS FOR A PARTICULAR PURPOSE.
8 : * See LICENSE in the root of the software repository for the full text of the License.
9 : */
10 :
11 : #ifndef HCCLV2_CCU_INSTRUCTION_ALL_REDUCE_NHR_1D_H_
12 : #define HCCLV2_CCU_INSTRUCTION_ALL_REDUCE_NHR_1D_H_
13 :
14 : #include "template_utils.h"
15 : #include "instruction.h"
16 : #include "ins_queue.h"
17 : #include "ccu_context_utils.h"
18 : #include "ccu_ctx_signature.h"
19 : #include "ccu_ins.h"
20 : #include "ccu_rank_group.h"
21 :
22 : namespace Hccl {
23 :
24 : using NHRStepInfo = struct NHRStepInfoDef {
25 : u32 step = 0;
26 : u32 myRank = 0;
27 : u32 nSlices;
28 : u32 toRank = 0;
29 : u32 fromRank = 0;
30 : std::vector<u32> txSliceIdxs;
31 : std::vector<u32> rxSliceIdxs;
32 :
33 0 : NHRStepInfoDef() : nSlices(0) {}
34 : };
35 :
36 : // 为AllReduceNHR1D实现的CCUIns、CCUCtxArg与CCUTaskArg
37 : class CcuCtxArgAllReduceNHR1D : public CcuCtxArg {
38 : public:
39 0 : explicit CcuCtxArgAllReduceNHR1D(
40 : const std::vector<uint64_t>& dimSize, uint32_t rankId, uint32_t axisId, uint32_t axisSize,
41 : const std::vector<NHRStepInfo> stepInfoVector, const std::map<u32, u32> indexMap, const CollAlgOperator& op,
42 : const std::vector<std::vector<RankId>>& tempVTopo)
43 0 : : dimSize_(dimSize),
44 0 : rankId_(rankId),
45 0 : axisId_(axisId),
46 0 : axisSize_(axisSize),
47 0 : stepInfoVector_(stepInfoVector),
48 0 : indexMap_(indexMap),
49 0 : op_(op),
50 0 : tempVTopo_(tempVTopo)
51 0 : {}
52 0 : CcuCtxSignature GetCtxSignature() const override
53 : {
54 0 : CcuCtxSignature signature;
55 0 : GenerateCcuCtxSignature(signature, CcuInstType::CCU_ALLREDUCE_NHR_1D_MEM2MEM, op_, tempVTopo_);
56 0 : return signature;
57 0 : }
58 : std::vector<uint64_t> dimSize_;
59 : uint32_t rankId_;
60 : uint32_t axisId_;
61 : uint32_t axisSize_;
62 : std::vector<NHRStepInfo> stepInfoVector_;
63 : std::map<u32, u32> indexMap_;
64 : CollAlgOperator op_;
65 : std::vector<std::vector<RankId>> tempVTopo_;
66 : };
67 :
68 : class CcuTaskArgAllReduceNHR1D : public CcuTaskArg {
69 : public:
70 0 : explicit CcuTaskArgAllReduceNHR1D(
71 : uint64_t inputAddr, uint64_t outputAddr, uint64_t token, uint64_t isInputOutputEqual, uint64_t die0Size,
72 : uint64_t die1Size, uint64_t die0SliceSize, uint64_t die1SliceSize, uint64_t die0LastSliceSize,
73 : uint64_t die1LastSliceSize)
74 0 : : inputAddr_(inputAddr),
75 0 : outputAddr_(outputAddr),
76 0 : token_(token),
77 0 : isInputOutputEqual_(isInputOutputEqual),
78 0 : die0Size_(die0Size),
79 0 : die1Size_(die1Size),
80 0 : die0SliceSize_(die0SliceSize),
81 0 : die1SliceSize_(die1SliceSize),
82 0 : die0LastSliceSize_(die0LastSliceSize),
83 0 : die1LastSliceSize_(die1LastSliceSize)
84 0 : {}
85 :
86 : uint64_t inputAddr_;
87 : uint64_t outputAddr_;
88 : uint64_t token_;
89 : uint64_t isInputOutputEqual_;
90 : uint64_t die0Size_;
91 : uint64_t die1Size_;
92 : uint64_t die0SliceSize_;
93 : uint64_t die1SliceSize_;
94 : uint64_t die0LastSliceSize_;
95 : uint64_t die1LastSliceSize_;
96 : };
97 :
98 : class CcuInstructionAllReduceNHR1D : public CcuInstruction {
99 : public:
100 0 : CcuInstructionAllReduceNHR1D() : CcuInstruction() {}
101 :
102 0 : void Init(
103 : uint32_t rankId, uint64_t inputAddr, uint64_t outputAddr, uint32_t axisId, uint32_t axisSize, uint64_t die0Size,
104 : uint64_t die1Size, uint64_t die0SliceSize, uint64_t die1SliceSize, uint64_t die0LastSliceSize,
105 : uint64_t die1LastSliceSize, std::vector<NHRStepInfo> stepInfoVector, std::map<u32, u32> indexMap,
106 : uint64_t token, uint64_t isInputOutputEqual, CollAlgOperator& op, std::vector<std::vector<RankId>>& tempVTopo)
107 : {
108 0 : u32 maxDimNum = 1;
109 0 : if (tempVTopo.size() != maxDimNum) {
110 0 : THROW<InvalidParamsException>(StringFormat(
111 : "[CcuInstructionAllReduceNHR1D] tempVTopo size is not 1, size is [%zu].", tempVTopo.size()));
112 : }
113 0 : dimSize_.push_back(tempVTopo[0].size());
114 0 : op_ = op;
115 0 : rankId_ = rankId;
116 0 : inputAddr_ = inputAddr;
117 0 : outputAddr_ = outputAddr;
118 0 : axisId_ = axisId;
119 0 : axisSize_ = axisSize;
120 0 : die0SliceSize_ = die0SliceSize;
121 0 : die1SliceSize_ = die1SliceSize;
122 0 : die0LastSliceSize_ = die0LastSliceSize;
123 0 : die1LastSliceSize_ = die1LastSliceSize;
124 0 : die0Size_ = die0Size;
125 0 : die1Size_ = die1Size;
126 0 : stepInfoVector_ = stepInfoVector;
127 0 : indexMap_ = indexMap;
128 0 : isInputOutputEqual_ = isInputOutputEqual;
129 0 : tempVTopo_ = tempVTopo;
130 0 : token_ = token;
131 0 : return;
132 : }
133 :
134 0 : CcuInstType GetInstType() const override
135 : {
136 0 : HCCL_INFO("CcuInstructionAllReduceNHR1D instype is CCU_ALLREDUCE_NHR_1D_MEM2MEM.");
137 0 : return instType_;
138 : }
139 :
140 0 : std::string Describe() const override
141 : {
142 : return StringFormat(
143 0 : "CcuInstructionAllReduceNHR1D rankId [%u], instType[%s]", rankId_, instType_.Describe().c_str());
144 : }
145 :
146 0 : std::unique_ptr<CcuCtxArg> GetCtxArg() const override
147 : {
148 0 : return std::make_unique<CcuCtxArgAllReduceNHR1D>(
149 0 : dimSize_, rankId_, axisId_, axisSize_, stepInfoVector_, indexMap_, op_, tempVTopo_);
150 : }
151 :
152 : void SetInstType(CcuInstType instType) { instType_ = instType; }
153 :
154 0 : std::unique_ptr<CcuTaskArg> GetTaskArg() const override
155 : {
156 0 : return std::make_unique<CcuTaskArgAllReduceNHR1D>(
157 0 : inputAddr_, outputAddr_, token_, isInputOutputEqual_, die0Size_, die1Size_, die0SliceSize_, die1SliceSize_,
158 0 : die0LastSliceSize_, die1LastSliceSize_);
159 : }
160 :
161 : private:
162 : CcuInstType instType_ = CcuInstType::CCU_ALLREDUCE_NHR_1D_MEM2MEM;
163 : std::vector<uint64_t> dimSize_;
164 : uint32_t rankId_{0};
165 : uint32_t axisId_{0};
166 : uint32_t axisSize_{0};
167 :
168 : uint64_t die0Size_{0};
169 : uint64_t die1Size_{0};
170 : uint64_t inputAddr_{0};
171 : uint64_t outputAddr_{0};
172 : uint64_t die1SliceSize_{0};
173 : uint64_t die0SliceSize_{0};
174 : uint64_t die0LastSliceSize_{0};
175 : uint64_t die1LastSliceSize_{0};
176 : uint64_t isInputOutputEqual_{0};
177 :
178 : std::vector<NHRStepInfo> stepInfoVector_;
179 : std::map<u32, u32> indexMap_;
180 : uint64_t token_{0};
181 : CollAlgOperator op_;
182 : std::vector<std::vector<RankId>> tempVTopo_;
183 : };
184 : } // namespace Hccl
185 :
186 : #endif // HCCLV2_CCU_INSTRUCTION_ALL_REDUCE_NHR_1D_H_
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