Line data Source code
1 : /**
2 : * Copyright (c) 2025 Huawei Technologies Co., Ltd.
3 : * This program is free software, you can redistribute it and/or modify it under the terms and conditions of
4 : * CANN Open Software License Agreement Version 2.0 (the "License").
5 : * Please refer to the License for details. You may not use this file except in compliance with the License.
6 : * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR IMPLIED,
7 : * INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY, OR FITNESS FOR A PARTICULAR PURPOSE.
8 : * See LICENSE in the root of the software repository for the full text of the License.
9 : */
10 :
11 : #include "aicpu/aicpu_hccl_sqcq.h"
12 : #include "adapter_hal_pub.h"
13 : #include "sal_pub.h"
14 : #include "hcomm_task_struct.h"
15 : #include "common/type_def.h"
16 :
17 : using char_t = char;
18 :
19 : extern "C" {
20 : drvError_t __attribute__((weak)) halCqReportRecv(uint32_t devId, struct halReportRecvInfo* info);
21 : drvError_t __attribute__((weak)) halSqCqQuery(uint32_t devId, struct halSqCqQueryInfo* info);
22 : drvError_t __attribute__((weak)) halSqCqConfig(uint32_t devId, struct halSqCqConfigInfo* info);
23 : drvError_t __attribute__((weak))
24 : halTsdrvCtl(uint32_t devId, int cmd, void* param, size_t paramSize, void* out, size_t* outSize);
25 : drvError_t __attribute__((weak)) halEschedSubmitEvent(uint32_t devId, struct event_summary* event);
26 : };
27 :
28 1104 : HcclResult QuerySqBaseAddr(uint32_t devId, uint32_t sqId, u64& outVal)
29 : {
30 1104 : CHK_PRT_RET(
31 : (halSqCqQuery == nullptr),
32 : HCCL_ERROR("halSqCqQuery is nullptr, "
33 : "Does not support this interface."),
34 : HCCL_E_DRV);
35 : halSqCqQueryInfo queryinfo;
36 1104 : queryinfo.tsId = 0;
37 1104 : queryinfo.sqId = sqId;
38 1104 : queryinfo.cqId = 0;
39 1104 : queryinfo.type = DRV_NORMAL_TYPE;
40 :
41 1104 : queryinfo.prop = DRV_SQCQ_PROP_SQ_BASE;
42 1104 : uint32_t ret = halSqCqQuery(devId, &queryinfo);
43 1104 : if (ret != 0) {
44 1 : HCCL_ERROR("halSqCqQuery base addr failed. ret = %d sqid:%d\n", ret, queryinfo.sqId);
45 1 : return HCCL_E_DRV;
46 : }
47 :
48 1103 : outVal = ((static_cast<u64>(queryinfo.value[1])) << UINT32_BIT_NUM) | queryinfo.value[0];
49 :
50 1103 : HCCL_DEBUG("valu1:%x. value0:%x, outValue:%p", queryinfo.value[1], queryinfo.value[0], outVal);
51 :
52 1103 : return HCCL_SUCCESS;
53 : }
54 :
55 797 : HcclResult QuerySqStatusByType(uint32_t devId, uint32_t sqId, drvSqCqPropType_t type, uint32_t& outVal)
56 : {
57 797 : CHK_PRT_RET(
58 : (halSqCqQuery == nullptr),
59 : HCCL_ERROR("halSqCqQuery is nullptr, "
60 : "Does not support this interface."),
61 : HCCL_E_DRV);
62 : halSqCqQueryInfo queryinfo;
63 797 : queryinfo.tsId = 0;
64 797 : queryinfo.sqId = sqId;
65 797 : queryinfo.cqId = 0;
66 797 : queryinfo.type = DRV_NORMAL_TYPE;
67 :
68 797 : queryinfo.prop = type;
69 797 : uint32_t ret = halSqCqQuery(devId, &queryinfo);
70 797 : if (ret != 0) {
71 2 : HCCL_ERROR("halSqCqQuery %d failed. ret = %d sqid:%d\n", type, ret, queryinfo.sqId);
72 2 : return HCCL_E_DRV;
73 : }
74 795 : outVal = queryinfo.value[0];
75 :
76 795 : return HCCL_SUCCESS;
77 : }
78 :
79 68 : HcclResult QuerySqStatus(uint32_t devId, uint32_t sqId, uint32_t& sqHead, uint32_t& sqTail)
80 : {
81 68 : HcclResult ret = QuerySqStatusByType(devId, sqId, DRV_SQCQ_PROP_SQ_TAIL, sqTail);
82 68 : if (ret != 0) {
83 1 : HCCL_ERROR(" halSqCqQuery TAIL failed. ret = %d sqid:%d\n", ret, sqId);
84 1 : return ret;
85 : }
86 :
87 67 : ret = QuerySqStatusByType(devId, sqId, DRV_SQCQ_PROP_SQ_HEAD, sqHead);
88 67 : if (ret != 0) {
89 0 : HCCL_ERROR(" halSqCqQuery HEAD failed. ret = %d sqid:%d\n", ret, sqId);
90 0 : return ret;
91 : }
92 :
93 67 : return ret;
94 : }
95 :
96 651 : HcclResult ConfigSqStatusByType(uint32_t devId, uint32_t sqId, drvSqCqPropType_t type, uint32_t value)
97 : {
98 651 : CHK_PRT_RET(
99 : (halSqCqConfig == nullptr),
100 : HCCL_ERROR("halSqCqConfig is nullptr, "
101 : "Does not support this interface."),
102 : HCCL_E_DRV);
103 : halSqCqConfigInfo configInfo;
104 651 : configInfo.tsId = 0;
105 651 : configInfo.sqId = sqId;
106 651 : configInfo.cqId = 0;
107 651 : configInfo.type = DRV_NORMAL_TYPE;
108 :
109 651 : configInfo.prop = type;
110 651 : configInfo.value[0] = value;
111 651 : uint32_t ret = halSqCqConfig(devId, &configInfo);
112 651 : if (ret != 0) {
113 1 : HCCL_ERROR(
114 : "halSqCqConfig %d failed. ret = %d sqid:%d, type:%d, value:%d", type, ret, configInfo.sqId, type, value);
115 1 : return HCCL_E_DRV;
116 : }
117 650 : return HCCL_SUCCESS;
118 : }
119 :
120 : namespace {
121 229 : void ConstructLHWI(const rtStarsCondIsaRegister_t dstReg, const u64 immd, rtStarsCondOpLHWI_t& opLHWI)
122 : {
123 229 : opLHWI.opCode = RT_STARS_COND_ISA_OP_CODE_LWI;
124 229 : opLHWI.func3 = RT_STARS_COND_ISA_LWI_FUNC3_LHWI;
125 229 : opLHWI.rd = dstReg;
126 229 : opLHWI.immd = static_cast<uint32_t>((immd >> 49U) & 0x7FFFU); // High15-immd[63:49]
127 229 : }
128 :
129 229 : void ConstructLLWI(const rtStarsCondIsaRegister_t dstReg, const u64 immd, rtStarsCondOpLLWI_t& opLLWI)
130 : {
131 229 : opLLWI.opCode = RT_STARS_COND_ISA_OP_CODE_LWI;
132 229 : opLLWI.func3 = RT_STARS_COND_ISA_LWI_FUNC3_LLWI;
133 229 : opLLWI.rd = dstReg;
134 229 : opLLWI.immdHigh = static_cast<uint32_t>((immd >> 32U) & 0x1FFFFU); // Low49-immd[48:32]
135 229 : opLLWI.immdLow = static_cast<uint32_t>(immd & 0xFFFFFFFFU); // Low49-immd[31:0]
136 229 : }
137 :
138 517 : void ConstructLoadImm(
139 : const rtStarsCondIsaRegister_t dstReg, const u64 addr, const rtStarsCondIsaLoadImmFunc3_t func3,
140 : rtStarsCondOpLoadImm_t& loadImm)
141 : {
142 517 : loadImm.opCode = RT_STARS_COND_ISA_OP_CODE_LOAD_IMM;
143 517 : loadImm.rd = dstReg;
144 517 : loadImm.func3 = func3;
145 517 : loadImm.immdAddrHigh = static_cast<uint32_t>((addr >> 32U) & 0X1FFFFU); // bit[48:32]
146 517 : loadImm.immdAddrLow = static_cast<uint32_t>(addr & 0xFFFFFFFFU); // bit[31:0]
147 517 : }
148 :
149 174 : void ConstructBranch(
150 : const rtStarsCondIsaRegister_t rs1Reg, const rtStarsCondIsaRegister_t rs2Reg,
151 : const rtStarsCondIsaBranchFunc3_t func3, const uint8_t instrOffset, rtStarsCondOpBranch_t& opBranch)
152 : {
153 174 : opBranch.opCode = RT_STARS_COND_ISA_OP_CODE_BRANCH;
154 174 : opBranch.func3 = func3;
155 174 : opBranch.rs1 = rs1Reg;
156 174 : opBranch.rs2 = rs2Reg;
157 174 : opBranch.jumpInstrOffset = instrOffset & 0xFU; // Jump-immd[3:0]
158 174 : }
159 :
160 229 : void ConstructStore(
161 : const rtStarsCondIsaRegister_t addrReg, const rtStarsCondIsaRegister_t valReg, const uint16_t immdOffset,
162 : const rtStarsCondIsaStoreFunc3_t func3, rtStarsCondOpStore_t& opStore)
163 : {
164 229 : opStore.opCode = RT_STARS_COND_ISA_OP_CODE_STORE;
165 229 : opStore.immdLow = static_cast<uint8_t>(immdOffset & 0x1FU); // S-immd[4:0]
166 229 : opStore.func3 = func3;
167 229 : opStore.rs1 = addrReg;
168 229 : opStore.rs2 = valReg;
169 229 : opStore.immdHigh = static_cast<uint8_t>((immdOffset & 0xFE0U) >> 5U); // S-immd[11:5]
170 229 : }
171 :
172 1992 : void ConstructNop(rtStarsCondOpNop_t& nop)
173 : {
174 1992 : nop.opCode = RT_STARS_COND_ISA_OP_CODE_NOP;
175 1992 : nop.rd = RT_STARS_COND_ISA_REGISTER_R0;
176 1992 : nop.func3 = RT_STARS_COND_ISA_OP_IMM_FUNC3_NOP;
177 1992 : nop.rs1 = RT_STARS_COND_ISA_REGISTER_R0;
178 1992 : nop.immd = 0U;
179 1992 : }
180 : } // namespace
181 :
182 174 : void AddOneWaitStartSqe(
183 : uint16_t streamId, uint16_t taskId, u64 waitAddr, u64 curTurnCntAddr, bool last,
184 : rtStarsCcoreWaitStartSqe_t* const sqe, uint8_t* sqeType)
185 : {
186 174 : *sqeType = SqeType::CCORE_WAIT_START_SQE;
187 174 : sqe->sqeHeader.type = RT_STARS_SQE_TYPE_COND;
188 174 : sqe->sqeHeader.rtStreamId = streamId;
189 174 : sqe->sqeHeader.taskId = taskId;
190 :
191 174 : sqe->kernel_credit = RT_STARS_DEFAULT_KERNEL_CREDIT;
192 174 : sqe->csc = 1U;
193 :
194 174 : constexpr rtStarsCondIsaRegister_t r0 = RT_STARS_COND_ISA_REGISTER_R0;
195 174 : constexpr rtStarsCondIsaRegister_t r1 = RT_STARS_COND_ISA_REGISTER_R1;
196 174 : constexpr rtStarsCondIsaRegister_t r2 = RT_STARS_COND_ISA_REGISTER_R2;
197 174 : constexpr rtStarsCondIsaRegister_t r3 = RT_STARS_COND_ISA_REGISTER_R3;
198 :
199 : // load current Turn to r3
200 174 : ConstructLoadImm(r3, curTurnCntAddr, RT_STARS_COND_ISA_LOAD_IMM_FUNC3_LHU, sqe->ldrImm1);
201 :
202 : // load sendcnt to r2
203 174 : ConstructLoadImm(r2, waitAddr, RT_STARS_COND_ISA_LOAD_IMM_FUNC3_LHU, sqe->ldrImm2);
204 174 : uint8_t loadInstrOff
205 : = (offsetof(rtStarsCcoreWaitStartSqe_t, ldrImm2) - offsetof(rtStarsCcoreWaitStartSqe_t, ldrImm1));
206 174 : loadInstrOff = loadInstrOff / sizeof(uint32_t);
207 :
208 : // r2(sendCnt) < r3(curTurn)，goto reload r2
209 174 : ConstructBranch(r2, r3, RT_STARS_COND_ISA_BRANCH_FUNC3_BLTU, loadInstrOff, sqe->beq);
210 :
211 174 : if (last) {
212 : // load sendcount addr to r1
213 60 : ConstructLLWI(r1, waitAddr, sqe->clear.llwi1);
214 60 : ConstructLHWI(r1, waitAddr, sqe->clear.lhwi1);
215 : // the last turn clear sendCnt, r0(0) value store to r1(sendCnt),
216 60 : ConstructStore(r1, r0, 0U, RT_STARS_COND_ISA_STORE_FUNC3_SH, sqe->clear.sw);
217 240 : for (rtStarsCondOpNop_t& nop : sqe->clear.nop) {
218 180 : ConstructNop(nop);
219 : }
220 : } else {
221 912 : for (rtStarsCondOpNop_t& nop : sqe->nop) {
222 798 : ConstructNop(nop);
223 : }
224 : }
225 :
226 174 : HCCL_INFO(
227 : "WaitStart waitAddr %p, curTurnCntAddr %p, loadInstrOff %u, streamId %u, taskId %u, last %u"
228 : "ISA: %08x %08x %08x %08x %08x %08x %08x.",
229 : waitAddr, curTurnCntAddr, loadInstrOff, streamId, taskId, last, sqe->ldrImm1, sqe->ldrImm2, sqe->beq,
230 : sqe->clear.llwi1, sqe->clear.lhwi1, sqe->clear.sw, sqe->clear.nop[0]);
231 174 : }
232 :
233 169 : void AddOneWriteValueStartSqe(
234 : uint16_t streamId, uint16_t taskId, u64 writeAddr, u64 valueAddr, rtStarsCcoreWriteValueSqe_t* const sqe,
235 : uint8_t* sqeType)
236 : {
237 169 : *sqeType = SqeType::CCORE_WRITE_VALUE_SQE;
238 169 : sqe->sqeHeader.type = RT_STARS_SQE_TYPE_COND;
239 169 : sqe->sqeHeader.rtStreamId = streamId;
240 169 : sqe->sqeHeader.taskId = taskId;
241 :
242 169 : sqe->kernel_credit = RT_STARS_DEFAULT_KERNEL_CREDIT;
243 169 : sqe->csc = 1U;
244 :
245 169 : constexpr rtStarsCondIsaRegister_t r1 = RT_STARS_COND_ISA_REGISTER_R1;
246 169 : constexpr rtStarsCondIsaRegister_t r2 = RT_STARS_COND_ISA_REGISTER_R2;
247 :
248 169 : ConstructLoadImm(r1, valueAddr, RT_STARS_COND_ISA_LOAD_IMM_FUNC3_LHU, sqe->ldrImm);
249 169 : ConstructLLWI(r2, writeAddr, sqe->llwi1);
250 169 : ConstructLHWI(r2, writeAddr, sqe->lhwi1);
251 :
252 169 : ConstructStore(r2, r1, 0U, RT_STARS_COND_ISA_STORE_FUNC3_SH, sqe->sw);
253 1183 : for (rtStarsCondOpNop_t& nop : sqe->nop) {
254 1014 : ConstructNop(nop);
255 : }
256 :
257 169 : HCCL_INFO(
258 : "CCore write value: writeAddr %p, valueAddr %p, streamId %u, taskId %u"
259 : "ISA: %08x %08x %08x %08x %08x.",
260 : writeAddr, valueAddr, streamId, taskId, sqe->ldrImm, sqe->llwi1, sqe->lhwi1, sqe->sw, sqe->nop[0]);
261 169 : }
262 :
263 25 : std::string StringLogicCqReportInfo(const rtLogicCqReport_t& reportOfOne)
264 : {
265 25 : std::stringstream ss;
266 25 : ss << "streamId :" << reportOfOne.streamId;
267 25 : ss << " taskId :" << reportOfOne.taskId;
268 25 : ss << " errorCode :" << reportOfOne.errorCode;
269 25 : ss << " errorType :" << static_cast<uint32_t>(reportOfOne.errorType);
270 25 : ss << " sqeType :" << static_cast<uint32_t>(reportOfOne.sqeType);
271 25 : ss << " sqId :" << reportOfOne.sqId;
272 25 : ss << " sqHead :" << reportOfOne.sqHead;
273 25 : ss << " matchFlag :" << reportOfOne.matchFlag;
274 25 : ss << " dropFlag :" << reportOfOne.dropFlag;
275 25 : ss << " errorBit :" << reportOfOne.errorBit;
276 25 : ss << " accError :" << reportOfOne.accError;
277 50 : return ss.str();
278 25 : }
279 :
280 13 : bool IsExceptionCqe(const rtLogicCqReport_t& reportOfOne)
281 : {
282 13 : HCCL_DEBUG("ReportOfOne info [%s]", StringLogicCqReportInfo(reportOfOne).c_str());
283 13 : if ((reportOfOne.errorType & RT_STARS_EXIST_ERROR) == 0U) { // 取低5位
284 1 : return false;
285 : }
286 12 : return true;
287 : }
288 :
289 29 : CqeStatus CqReportRecv(const CqeQueryInput& cqeQueryInput, rtLogicCqReport_t& cqeException)
290 : {
291 29 : CHK_PRT_RET(
292 : (halCqReportRecv == nullptr),
293 : HCCL_ERROR("halCqReportRecv is nullptr, "
294 : "Does not support this interface."),
295 : CqeStatus::kCqeInnerError);
296 : halReportRecvInfo recvInfo;
297 29 : recvInfo.type = static_cast<drvSqCqType_t>(cqeQueryInput.type);
298 29 : recvInfo.tsId = 0;
299 29 : recvInfo.report_cqe_num = 0;
300 29 : recvInfo.stream_id = cqeQueryInput.streamId;
301 29 : recvInfo.cqId = cqeQueryInput.cqId;
302 29 : recvInfo.timeout = 0; // 不设置超时时间，非阻塞
303 29 : recvInfo.task_id = 0xFFFF; // 接收所有类型
304 29 : recvInfo.cqe_addr = cqeQueryInput.cqeAddr; // 外部保证是有效的地址
305 29 : recvInfo.cqe_num = (recvInfo.type == DRV_LOGIC_TYPE ? AC_SQE_REV_MAX_CNT : MAX_REPORT_CNT);
306 29 : drvError_t ret = halCqReportRecv(cqeQueryInput.devId, &recvInfo);
307 29 : if (ret == DRV_ERROR_WAIT_TIMEOUT) {
308 3 : HCCL_DEBUG("halCqReportRecv has found nothing, ret:%d", ret);
309 3 : return CqeStatus::kCqeTimeOut;
310 : }
311 26 : if (ret != DRV_ERROR_NONE) {
312 3 : HCCL_ERROR("halCqReportRecv failed, ret:%d", ret);
313 3 : return CqeStatus::kCqeInnerError;
314 : }
315 23 : if (recvInfo.type != DRV_LOGIC_TYPE) { // 非DRV_LOGIC_TYPE不支持解析
316 0 : return CqeStatus::kDefault;
317 : }
318 23 : uint32_t reportNum = recvInfo.report_cqe_num;
319 23 : CHK_PRT_RET(
320 : reportNum > AC_SQE_REV_MAX_CNT,
321 : HCCL_ERROR(
322 : "report cqe num %u should "
323 : "not big than %u",
324 : reportNum, AC_SQE_REV_MAX_CNT),
325 : CqeStatus::kCqeUnknown);
326 24 : for (uint32_t idx = 0U; idx < reportNum; ++idx) {
327 13 : const auto& reportOfOne
328 13 : = *((reinterpret_cast<rtLogicCqReport_t*>(recvInfo.cqe_addr)) + idx); // 外部保证是有效的地址
329 13 : if (IsExceptionCqe(reportOfOne)) {
330 12 : HCCL_ERROR(
331 : "Task {%s} run failed of exception, idx:[%u], info:[%s]", cqeQueryInput.ToString().c_str(), idx,
332 : StringLogicCqReportInfo(reportOfOne).c_str());
333 12 : cqeException = reportOfOne;
334 12 : return CqeStatus::kCqeException;
335 : }
336 : }
337 11 : return CqeStatus::kDefault;
338 : }
339 :
340 4 : HcclResult StreamsKill(const uint32_t devId)
341 : {
342 4 : CHK_PRT_RET(
343 : (halTsdrvCtl == nullptr),
344 : HCCL_ERROR("halTsdrvCtl is nullptr, "
345 : "Does not support this interface."),
346 : HCCL_E_DRV);
347 4 : ts_ctrl_msg_body_t killIn = {};
348 4 : ts_ctrl_msg_body_t killAck = {};
349 4 : size_t ackCount = sizeof(ts_ctrl_msg_body_t);
350 4 : killIn.type = OP_ABORT_APP;
351 4 : struct tsdrv_ctrl_msg para = {};
352 4 : para.tsid = 0;
353 4 : para.msg_len = sizeof(ts_ctrl_msg_body_t);
354 4 : para.msg = static_cast<void*>(&killIn);
355 4 : const drvError_t ret = halTsdrvCtl(
356 : devId, TSDRV_CTL_CMD_CTRL_MSG, static_cast<void*>(¶), sizeof(tsdrv_ctrl_msg), static_cast<void*>(&killAck),
357 : &ackCount);
358 4 : if (ret != DRV_ERROR_NONE) {
359 2 : HCCL_ERROR("halTsdrvCtl failed. ret = %d\n", ret);
360 2 : return HCCL_E_DRV;
361 : }
362 2 : return HCCL_SUCCESS;
363 : }
364 :
365 3 : inline u64 GetCurCpuTimestamp()
366 : {
367 3 : constexpr u64 NSEC_PER_SEC = 1000000000U;
368 : struct timespec timestamp;
369 3 : (void)clock_gettime(CLOCK_MONOTONIC_RAW, ×tamp);
370 3 : return static_cast<u64>((timestamp.tv_sec * NSEC_PER_SEC) + (timestamp.tv_nsec));
371 : }
372 :
373 3 : HcclResult DeviceQuery(const uint32_t devId, const uint32_t step, const uint32_t timeout)
374 : {
375 3 : CHK_PRT_RET(
376 : (halTsdrvCtl == nullptr),
377 : HCCL_ERROR("halTsdrvCtl is nullptr, "
378 : "Does not support this interface."),
379 : HCCL_E_DRV);
380 : uint32_t status;
381 : uint64_t endTime;
382 3 : const uint64_t startTime = GetCurCpuTimestamp();
383 3 : bool flag = true;
384 3 : while (flag) {
385 3 : ts_ctrl_msg_body_t queryIn = {};
386 3 : ts_ctrl_msg_body_t queryAck = {};
387 3 : size_t ackCount = sizeof(ts_ctrl_msg_body_t);
388 3 : queryIn.type = OP_QUERY_ABORT_STATUS;
389 3 : queryIn.u.query_task_info.choice = APP_ABORT_STS_QUERY_BY_PID;
390 3 : struct tsdrv_ctrl_msg para = {};
391 3 : para.tsid = 0;
392 3 : para.msg_len = sizeof(ts_ctrl_msg_body_t);
393 3 : para.msg = static_cast<void*>(&queryIn);
394 3 : const drvError_t ret = halTsdrvCtl(
395 : devId, TSDRV_CTL_CMD_CTRL_MSG, static_cast<void*>(¶), sizeof(tsdrv_ctrl_msg),
396 : static_cast<void*>(&queryAck), &ackCount);
397 3 : if ((ret != DRV_ERROR_NONE) || (ackCount != sizeof(ts_ctrl_msg_body_t))) {
398 1 : HCCL_ERROR("halTsdrvCtl failed. ret = %d\n", ret);
399 1 : return HCCL_E_DRV;
400 : }
401 :
402 2 : status = queryAck.u.query_task_ack_info.status;
403 2 : if (status >= step) {
404 2 : flag = false;
405 2 : break;
406 : }
407 0 : endTime = GetCurCpuTimestamp();
408 0 : if ((timeout != 0U) && ((endTime - startTime) > timeout)) {
409 0 : HCCL_ERROR("kill query timeout.\n");
410 0 : return HCCL_E_TIMEOUT;
411 : }
412 0 : SaluSleep(5000U);
413 : }
414 2 : return HCCL_SUCCESS;
415 : }
416 :
417 : namespace hccl_plf {
418 : // 把SDMA类错误码转换成Ts对应的错误码
419 0 : uint16_t SwitchSdmaCqeErrCodeToTsErrCode(u32 cqeErrCode)
420 : {
421 0 : switch (cqeErrCode) {
422 0 : case RT_SDMA_COMPERR:
423 0 : return TS_ERROR_SDMA_LINK_ERROR;
424 0 : case RT_SDMA_COMPDATAERR:
425 0 : return TS_ERROR_SDMA_POISON_ERROR;
426 0 : case RT_SDMA_DATAERR:
427 0 : return TS_ERROR_SDMA_DDRC_ERROR;
428 0 : case TS_ERROR_RETRY_CONSTRAINT:
429 0 : return TS_ERROR_RETRY_CONSTRAINT;
430 0 : default:
431 0 : return TS_ERROR_HCCL_OTHER_ERROR;
432 : }
433 : }
434 :
435 0 : HcclResult SendTaskExceptionByMBox(
436 : const u32 localDeviceId, const u32 notifyId, const u32 tsId, const s32 userStreamId, const u32 cqeErrCode)
437 : {
438 0 : CHK_PRT_RET(
439 : (halEschedSubmitEvent == nullptr),
440 : HCCL_ERROR("halEschedSubmitEvent is nullptr, "
441 : "Does not support this interface."),
442 : HCCL_E_DRV);
443 0 : ts_aicpu_sqe_t aicpuSqe = {};
444 0 : u32 hostpid = 0;
445 0 : u32 vf_id = 0;
446 : // 调整drvQueryProcessHostPid获取pid和vf_id的值
447 0 : CHK_RET(HrtHalDrvQueryProcessHostPid(getpid(), nullptr, &vf_id, &hostpid, nullptr));
448 :
449 0 : aicpuSqe.pid = hostpid;
450 0 : aicpuSqe.cmd_type = AICPU_RECORD;
451 0 : aicpuSqe.vf_id = vf_id;
452 0 : aicpuSqe.tid = 0U; // notify is no need tid
453 0 : aicpuSqe.u.aicpu_record.record_type = AICPU_MSG_NOTIFY_RECORD;
454 0 : aicpuSqe.u.aicpu_record.record_id = notifyId;
455 :
456 0 : aicpuSqe.ts_id = static_cast<uint8_t>(tsId);
457 :
458 0 : aicpuSqe.u.aicpu_record.fault_stream_id = static_cast<uint16_t>(userStreamId);
459 :
460 0 : aicpuSqe.u.aicpu_record.ret_code = SwitchSdmaCqeErrCodeToTsErrCode(cqeErrCode);
461 :
462 0 : struct event_summary event = {};
463 0 : event.dst_engine = TS_CPU;
464 0 : event.policy = ONLY;
465 0 : event.pid = 0;
466 0 : event.grp_id = 0;
467 0 : event.event_id = EVENT_TS_CTRL_MSG;
468 0 : event.subevent_id = 0U;
469 0 : event.msg_len = static_cast<uint32_t>(sizeof(ts_aicpu_sqe_t));
470 0 : event.msg = PtrToPtr<ts_aicpu_sqe_t, char_t>(&aicpuSqe);
471 0 : auto ret = halEschedSubmitEvent(localDeviceId, &event);
472 0 : if (ret != static_cast<int32_t>(DRV_ERROR_NONE)) {
473 0 : HCCL_ERROR(
474 : "[SendTaskExceptionByMBox]Send msg async to ts failed. ret=%d, streamId=%d, "
475 : "notifyId=%u.",
476 : ret, userStreamId, notifyId);
477 0 : return HCCL_E_DRV;
478 : }
479 0 : HCCL_RUN_INFO(
480 : "[SendTaskExceptionByMBox]Send msg async to ts finished. streamId=%d, notifyId=%u, msg_size=%u, "
481 : "hostpid=%u, vf_id=%u, errCode=%u.",
482 : userStreamId, notifyId, static_cast<uint32_t>(sizeof(ts_aicpu_sqe_t)), hostpid, vf_id, cqeErrCode);
483 0 : return HCCL_SUCCESS;
484 : }
485 : } // namespace hccl_plf
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