Line data Source code
1 : /**
2 : * Copyright (c) 2025 Huawei Technologies Co., Ltd.
3 : * This program is free software, you can redistribute it and/or modify it under the terms and conditions of
4 : * CANN Open Software License Agreement Version 2.0 (the "License").
5 : * Please refer to the License for details. You may not use this file except in compliance with the License.
6 : * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR IMPLIED,
7 : * INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY, OR FITNESS FOR A PARTICULAR PURPOSE.
8 : * See LICENSE in the root of the software repository for the full text of the License.
9 : */
10 :
11 : #include "all_gather_v_graph_pipeline.h"
12 : #include "alg_template_register.h"
13 :
14 : constexpr u32 STEP_OFFSET_TWO = 2;
15 :
16 : namespace hccl {
17 0 : AllGatherVGraphPipeline::AllGatherVGraphPipeline(const HcclDispatcher dispatcher) : AllGatherVPipeline(dispatcher) {}
18 :
19 0 : HcclResult AllGatherVGraphPipeline::RunAsync()
20 : {
21 0 : HCCL_INFO("[AllGatherVGraphPipeline][RunAsync]AllGatherRingMesh starts groupRankId[%u] ", userRank_);
22 :
23 0 : u32 unitSize = SIZE_TABLE[opInfo_->dataType];
24 :
25 : // step 0前置操作 : 所有卡本地数据从userIn-->userout
26 0 : DeviceMem locSrc = DeviceMem::create(usrInMemAddr_, memSliceCount_ * unitSize);
27 0 : u64 localOffset = userMemSlice_[userRank_].offset;
28 : DeviceMem locDst = DeviceMem::create(
29 0 : static_cast<void*>(static_cast<u8*>(dmaMem_[1].ptr()) + localOffset), memSliceCount_ * unitSize);
30 0 : CHK_RET(HcclD2DMemcpyAsync(dispatcher_, locDst, locSrc, stream_));
31 :
32 0 : for (u32 step = 0; step < interRankSize_; step++) {
33 0 : CHK_RET(MainRecordSub());
34 0 : CHK_RET(SubWaitMain());
35 0 : CHK_RET(ExecInterServer(step));
36 0 : CHK_RET(ExecIntraServer(step));
37 0 : CHK_RET(SubRecordMain());
38 0 : CHK_RET(MainWaitSub());
39 : }
40 :
41 0 : HCCL_INFO("[AllGatherVGraphPipeline][RunAsync]AllGatherVGraphPipeline finished groupRankId[%u] ", userRank_);
42 0 : return HCCL_SUCCESS;
43 0 : }
44 :
45 0 : HcclResult AllGatherVGraphPipeline::ExecInterServer(u32 step)
46 : {
47 : // inter ring algo
48 0 : u32 prevInterRankId = (interRankId_ - 1 + interRankSize_) % interRankSize_;
49 0 : u32 nextInterRankId = (interRankId_ + 1) % interRankSize_;
50 0 : LINK prevInterLink = interLinks_[prevInterRankId];
51 0 : LINK nextInterLink = interLinks_[nextInterRankId];
52 0 : u64 serverRankOffset = intraRankId_ + (interRankId_ + interRankSize_ - step) % interRankSize_ * intraRankSize_;
53 0 : u64 serverOffsetByte = userMemSlice_[serverRankOffset].offset;
54 0 : u64 readRemoteOffset
55 0 : = intraRankId_
56 0 : + (prevInterRankId + interRankSize_ - step) % interRankSize_ * intraRankSize_; // sever间前通信rank偏移
57 0 : u64 readRemoteOffsetByte = userMemSlice_[readRemoteOffset].offset;
58 0 : if (step < interRankSize_ - 1) {
59 0 : CHK_RET(prevInterLink->TxAck(subStream_[0])); // AckRecord
60 0 : CHK_RET(nextInterLink->RxAck(subStream_[0])); // AckWait
61 : // RdmaSend + Record 或 PCIE::Record
62 0 : CHK_RET(nextInterLink->TxAsync(
63 : UserMemType::OUTPUT_MEM, serverOffsetByte, static_cast<u8*>(dmaMem_[1].ptr()) + serverOffsetByte,
64 : userMemSlice_[serverRankOffset].size, subStream_[0]));
65 0 : HCCL_DEBUG(
66 : "[AllGatherVGraphPipeline][RunAsync] local rank[%u] localOffset[%llu]tx with remoteRank[%u],"
67 : "remoteOffset[%llu] with slice[%llu]",
68 : userRank_, serverOffsetByte, nextInterRankId, serverOffsetByte, userMemSlice_[serverRankOffset].size);
69 : // 对于RDMA RxAsync,内存属性入参无效 RDMA::Wait
70 : // 对于PCIE,需设置内存属性 PCIE::Read + Record
71 0 : CHK_RET(prevInterLink->RxAsync(
72 : UserMemType::OUTPUT_MEM, readRemoteOffsetByte, static_cast<u8*>(dmaMem_[1].ptr()) + readRemoteOffsetByte,
73 : userMemSlice_[readRemoteOffset].size, subStream_[0])); // wait
74 0 : HCCL_DEBUG(
75 : "[AllGatherVGraphPipeline][RunAsync]read local rank[%u] localOffset[%llu]tx with remoteRank[%u],"
76 : "remoteOffset[%llu] with slice[%llu]",
77 : userRank_, readRemoteOffsetByte, readRemoteOffset, readRemoteOffsetByte,
78 : userMemSlice_[readRemoteOffset].size);
79 0 : CHK_RET(prevInterLink->PostFinAck(subStream_[0]));
80 0 : CHK_RET(nextInterLink->WaitFinAck(subStream_[0]));
81 : // inter的最后一步需要barrier确保数据发完
82 0 : if (step == interRankSize_ - STEP_OFFSET_TWO) {
83 0 : CHK_RET(ExecuteBarrier(prevInterLink, nextInterLink, subStream_[0]));
84 : }
85 : }
86 0 : return HCCL_SUCCESS;
87 0 : }
88 :
89 0 : HcclResult AllGatherVGraphPipeline::ExecIntraServer(u32 step)
90 : {
91 0 : for (u32 i = 1; i < intraRankSize_; i++) {
92 0 : u32 remIntraRankId = (intraRankId_ + i) % intraRankSize_;
93 0 : CHK_RET(intraLinks_[remIntraRankId]->TxAck(subStream_[i])); // ackrecord
94 0 : CHK_RET(intraLinks_[remIntraRankId]->RxAck(subStream_[i])); // ackwait
95 :
96 0 : void* remDMAMemPtr = nullptr;
97 0 : CHK_RET(intraLinks_[remIntraRankId]->GetRemoteMem(UserMemType::OUTPUT_MEM, &remDMAMemPtr));
98 0 : u64 remoteRankOffset
99 0 : = (interRankId_ - step + interRankSize_) % interRankSize_ * intraRankSize_ + remIntraRankId;
100 0 : u64 remoteOffsetByte = userMemSlice_[remoteRankOffset].offset;
101 0 : void* dstAddr = static_cast<u8*>(usrOutMemAddr_) + remoteOffsetByte;
102 :
103 : DeviceMem src = DeviceMem::create(
104 0 : static_cast<u8*>(remDMAMemPtr) + remoteOffsetByte, userMemSlice_[remoteRankOffset].size);
105 0 : DeviceMem dst = DeviceMem::create(dstAddr, userMemSlice_[remoteRankOffset].size);
106 0 : CHK_RET(HcclD2DMemcpyAsync(dispatcher_, dst, src, subStream_[i]));
107 :
108 0 : CHK_RET(intraLinks_[remIntraRankId]->TxDataSignal(subStream_[i])); // data record
109 0 : CHK_RET(intraLinks_[remIntraRankId]->RxDataSignal(subStream_[i])); // data wait
110 0 : }
111 0 : return HCCL_SUCCESS;
112 : }
113 :
114 : REGISTER_TEMPLATE(TemplateType::TEMPLATE_ALL_GATHER_V_GRAPH_PIPELINE, AllGatherVGraphPipeline);
115 : } // namespace hccl
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