Line data Source code
1 : /**
2 : * Copyright (c) 2025 Huawei Technologies Co., Ltd.
3 : * This program is free software, you can redistribute it and/or modify it under the terms and conditions of
4 : * CANN Open Software License Agreement Version 2.0 (the "License").
5 : * Please refer to the License for details. You may not use this file except in compliance with the License.
6 : * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR IMPLIED,
7 : * INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY, OR FITNESS FOR A PARTICULAR PURPOSE.
8 : * See LICENSE in the root of the software repository for the full text of the License.
9 : */
10 : #ifndef MEM_TRANSPORT_LITE_H
11 : #define MEM_TRANSPORT_LITE_H
12 : #include <vector>
13 : #include <memory>
14 : #include <unordered_map>
15 : #include <functional>
16 : #include "task_param.h"
17 : #include "base_transport_lite_impl.h"
18 : #include "stream_lite.h"
19 : #include "rma_buffer_lite.h"
20 : #include "buffer.h"
21 : #include "kernel_param_lite.h"
22 :
23 : namespace Hccl {
24 :
25 : class MemTransportLite {
26 : public:
27 : explicit MemTransportLite(std::vector<char> &uniqueId,
28 : std::function<void(u32 streamId, u32 taskId, const TaskParam &taskParam)> callback);
29 :
30 : std::string Describe() const;
31 :
32 : using TransferOp = struct TransferOp;
33 :
34 11 : Buffer GetRmtBuffer(u32 index)
35 : {
36 11 : return impl->GetRmtBuffer(index);
37 : }
38 :
39 6 : void Post(u32 index, const StreamLite &stream)
40 : {
41 6 : impl->Post(index, stream);
42 6 : }
43 :
44 4 : void Wait(u32 index, const StreamLite &stream)
45 : {
46 4 : impl->Wait(index, stream);
47 4 : }
48 :
49 2 : void Read(const RmaBufferLite &loc, const Buffer &rmt, const StreamLite &stream)
50 : {
51 2 : impl->Read(loc, rmt, stream);
52 2 : }
53 :
54 3 : void Write(const RmaBufferLite &loc, const Buffer &rmt, const StreamLite &stream)
55 : {
56 3 : impl->Write(loc, rmt, stream);
57 3 : }
58 :
59 2 : void ReadReduce(const RmaBufferLite &loc, const Buffer &rmt, const ReduceIn &reduceIn, const StreamLite &stream)
60 : {
61 2 : impl->ReadReduce(loc, rmt, reduceIn, stream);
62 2 : }
63 :
64 2 : void WriteReduce(const RmaBufferLite &loc, const Buffer &rmt, const ReduceIn &reduceIn, const StreamLite &stream)
65 : {
66 2 : impl->WriteReduce(loc, rmt, reduceIn, stream);
67 2 : }
68 :
69 3 : void WriteWithNotify(const RmaBufferLite &loc, const Buffer &rmt, const WithNotifyIn &withNotify,
70 : const StreamLite &stream)
71 : {
72 3 : impl->WriteWithNotify(loc, rmt, withNotify, stream);
73 3 : }
74 :
75 1 : void WriteReduceWithNotify(const RmaBufferLite &loc, const Buffer &rmt, const ReduceIn &reduceIn,
76 : const WithNotifyIn &withNotify, const StreamLite &stream)
77 : {
78 1 : impl->WriteReduceWithNotify(loc, rmt, reduceIn, withNotify, stream);
79 1 : }
80 :
81 1 : void BatchOneSidedRead(const std::vector<RmaBufSliceLite> &loc, const std::vector<RmtRmaBufSliceLite> &rmt, const StreamLite &stream)
82 : {
83 1 : impl->BatchOneSidedRead(loc, rmt, stream);
84 1 : }
85 :
86 1 : void BatchOneSidedWrite(const std::vector<RmaBufSliceLite> &loc, const std::vector<RmtRmaBufSliceLite> &rmt, const StreamLite &stream)
87 : {
88 1 : impl->BatchOneSidedWrite(loc, rmt, stream);
89 1 : }
90 :
91 3 : void BatchTransfer(const std::vector<RmaBufferLite> &loc, const std::vector<Buffer> &rmt,
92 : const std::vector<BaseTransportLiteImpl::TransferOp> &transferOp, const StreamLite &stream)
93 : {
94 3 : impl->BatchTransfer(loc, rmt, transferOp, stream);
95 3 : }
96 :
97 : private:
98 : TransportType type;
99 :
100 : std::unique_ptr<BaseTransportLiteImpl> impl;
101 : };
102 :
103 : } // namespace Hccl
104 : #endif
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