Line data Source code
1 : /**
2 : * Copyright (c) 2025 Huawei Technologies Co., Ltd.
3 : * This program is free software, you can redistribute it and/or modify it under the terms and conditions of
4 : * CANN Open Software License Agreement Version 2.0 (the "License").
5 : * Please refer to the License for details. You may not use this file except in compliance with the License.
6 : * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR IMPLIED,
7 : * INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY, OR FITNESS FOR A PARTICULAR PURPOSE.
8 : * See LICENSE in the root of the software repository for the full text of the License.
9 : */
10 : #ifndef HCCLV2_RMA_CONN_LITE_H
11 : #define HCCLV2_RMA_CONN_LITE_H
12 : #include <memory>
13 : #include "rma_buf_slice_lite.h"
14 : #include "rmt_rma_buf_slice_lite.h"
15 : #include "log.h"
16 : #include "reduce_in.h"
17 : #include "data_type.h"
18 : #include "reduce_op.h"
19 : #include "ip_address.h"
20 : #include "ub_jetty_lite.h"
21 : #include "kernel_param_lite.h"
22 : #include "stream_lite.h"
23 : namespace Hccl {
24 : MAKE_ENUM(RmaConnLiteType, P2P, RDMA, UB, CCU) // 需要和RmaConnType一一对应
25 :
26 : struct SqeConfigLite {
27 39 : SqeConfigLite() : placeOdr(1), compOrder(1), fence(1) {}
28 : bool cqeEn{true};
29 : bool userConfig{false};
30 : u8 placeOdr : 2;
31 : u8 compOrder : 1;
32 : u8 fence : 1;
33 : };
34 :
35 : struct ConnLiteOperationOut {
36 : u16 pi{0};
37 : u8 *data{};
38 : u8 dataSize{0};
39 : };
40 :
41 : class RmaConnLite {
42 : public:
43 53 : RmaConnLite() = default;
44 :
45 : RmaConnLite(const UbJettyLiteId &id, const UbJettyLiteAttr &attr, const Eid &rmtEid);
46 :
47 : explicit RmaConnLite(const u64 qpVa);
48 :
49 79 : virtual ~RmaConnLite() = default;
50 :
51 : static std::unique_ptr<RmaConnLite> Create(std::vector<char> &uniqueId);
52 :
53 : UbJettyLiteId GetUbJettyLiteId() const;
54 :
55 : UbJettyLiteAttr GetUbJettyLiteAttr() const;
56 :
57 : Eid GetRmtEid() const;
58 : Eid GetLocEid() const;
59 :
60 : u32 GetQpVa() const;
61 : uint64_t GetJettyHandle() const;
62 : uint32_t GetJettyId() const;
63 :
64 : virtual std::string Describe();
65 :
66 2 : virtual void Read(const RmaBufSliceLite &loc, const RmtRmaBufSliceLite &rmt, const SqeConfigLite &cfg,
67 : const StreamLite &stream, ConnLiteOperationOut &out)
68 : {
69 6 : HCCL_INFO("RmaConnLite read start. loc.addr = %llx, rmt.addr = %llx, cfg.cqeEn = %u, out.pi = %u",
70 : loc.GetAddr(), rmt.GetAddr(), cfg.cqeEn, out.pi);
71 2 : }
72 :
73 1 : virtual void ReadReduce(ReduceIn reduceIn, const RmaBufSliceLite &loc, const RmtRmaBufSliceLite &rmt,
74 : const StreamLite &stream, const SqeConfigLite &cfg, ConnLiteOperationOut &out)
75 : {
76 3 : HCCL_INFO("RmaConnLite ReadReduce start. dataType = %u, reduceOp %u, loc.addr = %llx, "
77 : "rmt.addr = %llx, cfg.cqeEn = %u, out.pi = %u",
78 : reduceIn.dataType, reduceIn.reduceOp, loc.GetAddr(), rmt.GetAddr(), cfg.cqeEn, out.pi);
79 1 : }
80 :
81 1 : virtual void Write(const RmaBufSliceLite &loc, const RmtRmaBufSliceLite &rmt, const SqeConfigLite &cfg,
82 : const StreamLite &stream, ConnLiteOperationOut &out)
83 : {
84 3 : HCCL_INFO("RmaConnLite write start. loc.addr = %llx, rmt.addr = %llx, cfg.cqeEn = %u, out.pi = %u",
85 : loc.GetAddr(), rmt.GetAddr(), cfg.cqeEn, out.pi);
86 1 : }
87 :
88 1 : virtual void InlineWrite(const u8 *data, u16 size, const RmtRmaBufSliceLite &rmt, const SqeConfigLite &cfg,
89 : const StreamLite &stream, ConnLiteOperationOut &out)
90 : {
91 3 : HCCL_INFO("RmaConnLite InlineWrite start. data = %p, size = %hu, rmt.addr = %llx, cfg.cqeEn = %u, out.pi = %u",
92 : data, size, rmt.GetAddr(), cfg.cqeEn, out.pi);
93 1 : }
94 :
95 1 : virtual void WriteReduce(DataType dataType, ReduceOp reduceOp, const RmaBufSliceLite &loc, const StreamLite &stream,
96 : const RmtRmaBufSliceLite &rmt, const SqeConfigLite &cfg, ConnLiteOperationOut &out)
97 : {
98 3 : HCCL_INFO("RmaConnLite WriteReduce start. dataType = %u, reduceOp %u, loc.addr = %llx, "
99 : "rmt.addr = %llx, cfg.cqeEn = %u, out.pi = %u",
100 : dataType, reduceOp, loc.GetAddr(), rmt.GetAddr(), cfg.cqeEn, out.pi);
101 1 : }
102 :
103 1 : virtual void WriteWithNotify(const RmaBufSliceLite &loc, const RmtRmaBufSliceLite &rmt, const SqeConfigLite &cfg,
104 : ConnLiteOperationOut &out, const RmtRmaBufSliceLite ¬ify, const StreamLite &stream,
105 : u64 notifyData)
106 : {
107 3 : HCCL_INFO("RmaConnLite WriteWithNotify start. loc.addr = %llx, rmt.addr = %llx, cfg.cqeEn = %u, "
108 : "out.pi = %u, notify.addr = %llx, notifyData = %u",
109 : loc.GetAddr(), rmt.GetAddr(), cfg.cqeEn, out.pi, notify.GetAddr(), notifyData);
110 1 : }
111 :
112 0 : virtual void WriteReduceWithNotify(DataType dataType, ReduceOp reduceOp, const RmaBufSliceLite &loc,
113 : const RmtRmaBufSliceLite &rmt, const SqeConfigLite &cfg, const StreamLite &stream,
114 : ConnLiteOperationOut &out, const RmtRmaBufSliceLite ¬ify, u64 notifyData)
115 : {
116 0 : HCCL_INFO("RmaConnLite WriteReduceWithNotify start. dataType = %d, , reduceOp %d, loc.addr = %llx, "
117 : "rmt.addr = %llx, cfg.cqeEn = %u, out.pi = %u, notify.addr = %llx, notifyData = %llu",
118 : dataType, reduceOp, loc.GetAddr(), rmt.GetAddr(), cfg.cqeEn, out.pi, notify.GetAddr(), notifyData);
119 0 : }
120 :
121 1 : virtual void BatchOneSidedRead(const vector<RmaBufSliceLite> &loc, const vector<RmtRmaBufSliceLite> &rmt, const SqeConfigLite &cfg,
122 : const StreamLite &stream, ConnLiteOperationOut &out)
123 : {
124 3 : HCCL_INFO("RmaConnLite BatchOneSidedRead start. loc.size = %llu, rmt.size = %llu, cfg.cqeEn = %u, out.pi = %u",
125 : loc.size(), rmt.size(), cfg.cqeEn, out.pi);
126 1 : }
127 :
128 1 : virtual void BatchOneSidedWrite(const vector<RmaBufSliceLite> &loc, const vector<RmtRmaBufSliceLite> &rmt, const SqeConfigLite &cfg,
129 : const StreamLite &stream, ConnLiteOperationOut &out)
130 : {
131 3 : HCCL_INFO("RmaConnLite BatchOneSidedWrite start. loc.size = %llu, rmt.size = %llu, cfg.cqeEn = %u, out.pi = %u",
132 : loc.size(), rmt.size(), cfg.cqeEn, out.pi);
133 1 : }
134 :
135 : protected:
136 : u32 qpVa_{0};
137 :
138 : u32 dieId_{0};
139 : u32 funcId_{0};
140 : u32 jettyId_{0};
141 : u64 dbAddr_{0};
142 : u64 sqVa_{0};
143 : u32 sqDepth_{0};
144 : bool dwqeCacheLocked_{false}; // direct WQE cache Lock
145 : u32 jfcPollMode_{0}; // 0代表STARS POLL， 1代表软件Poll
146 : u32 tpn_{0};
147 :
148 : Eid rmtEid_;
149 : Eid locEid_;
150 : uint64_t jettyHandle_{0};
151 : };
152 :
153 : } // namespace Hccl
154 : #endif
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