Line data Source code
1 : /**
2 : * Copyright (c) 2025 Huawei Technologies Co., Ltd.
3 : * This program is free software, you can redistribute it and/or modify it under the terms and conditions of
4 : * CANN Open Software License Agreement Version 2.0 (the "License").
5 : * Please refer to the License for details. You may not use this file except in compliance with the License.
6 : * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR IMPLIED,
7 : * INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY, OR FITNESS FOR A PARTICULAR PURPOSE.
8 : * See LICENSE in the root of the software repository for the full text of the License.
9 : */
10 : #include "sqe_build_a5.h"
11 : #include "communicator_impl_lite_manager.h"
12 :
13 : namespace Hccl {
14 :
15 1 : u32 GetKernelExecTimeoutFromEnvConfig()
16 : {
17 1 : const u32 envTimeout = CommunicatorImplLiteMgr::GetInstance().GetEnvConfig().hcclExecTimeout;
18 1 : return envTimeout;
19 : }
20 :
21 : namespace
22 : {
23 1 : void ConstructLHWI(const Rt91095StarsCondIsaRegister_t dstReg, const u64 immd, Rt91095StarsCondOpLHWI_t &opLHWI)
24 : {
25 1 : opLHWI.opCode = static_cast<uint32_t>(Hccl::Rt91095StarsCondIsaOpCode_t::RT_91095_STARS_COND_ISA_OP_CODE_LWI);
26 1 : opLHWI.func3 = static_cast<uint32_t>(Rt91095StarsCondIsaLwiFunc3_t::RT_91095_STARS_COND_ISA_LWI_FUNC3_LHWI);
27 1 : opLHWI.rd = static_cast<uint32_t>(dstReg);
28 1 : opLHWI.immd = static_cast<uint32_t>((immd >> 49U) & 0x7FFFU); // High15-immd[63:49]
29 1 : }
30 :
31 1 : void ConstructLLWI(const Rt91095StarsCondIsaRegister_t dstReg, const u64 immd, Rt91095StarsCondOpLLWI_t &opLLWI)
32 : {
33 1 : opLLWI.opCode = static_cast<uint32_t>(Rt91095StarsCondIsaOpCode_t::RT_91095_STARS_COND_ISA_OP_CODE_LWI);
34 1 : opLLWI.func3 = static_cast<uint32_t>(Rt91095StarsCondIsaLwiFunc3_t::RT_91095_STARS_COND_ISA_LWI_FUNC3_LLWI);
35 1 : opLLWI.rd = static_cast<uint32_t>(dstReg);
36 1 : opLLWI.immdHigh = static_cast<uint32_t>((immd >> 32U) & 0x1FFFFU); // Low49-immd[48:32]
37 1 : opLLWI.immdLow = static_cast<uint32_t>(immd & 0xFFFFFFFFU); // Low49-immd[31:0]
38 1 : }
39 :
40 3 : void ConstructLoadImm(const Rt91095StarsCondIsaRegister_t dstReg, const u64 addr,
41 : const Rt91095StarsCondIsaLoadImmFunc3_t func3, Rt91095StarsCondOpLoadImm_t &loadImm)
42 : {
43 3 : loadImm.opCode = static_cast<uint32_t>(Rt91095StarsCondIsaOpCode_t::RT_91095_STARS_COND_ISA_OP_CODE_LOAD_IMM);
44 3 : loadImm.rd = static_cast<uint32_t>(dstReg);
45 3 : loadImm.func3 = static_cast<uint32_t>(func3);
46 3 : loadImm.immdAddrHigh = static_cast<uint32_t>((addr >> 32U) & 0X1FFFFU); // bit[48:32]
47 3 : loadImm.immdAddrLow = static_cast<uint32_t>(addr & 0xFFFFFFFFU); // bit[31:0]
48 3 : }
49 :
50 1 : void ConstructBranch(const Rt91095StarsCondIsaRegister_t rs1Reg, const Rt91095StarsCondIsaRegister_t rs2Reg,
51 : const Rt91095StarsCondIsaBranchFunc3_t func3, const uint8_t instrOffset,
52 : Rt91095StarsCondOpBranch_t &opBranch)
53 : {
54 1 : opBranch.opCode = static_cast<uint32_t>(Rt91095StarsCondIsaOpCode_t::RT_91095_STARS_COND_ISA_OP_CODE_BRANCH);
55 1 : opBranch.func3 = static_cast<uint32_t>(func3);
56 1 : opBranch.rs1 = static_cast<uint32_t>(rs1Reg);
57 1 : opBranch.rs2 = static_cast<uint32_t>(rs2Reg);
58 1 : opBranch.jumpInstrOffset = instrOffset & 0xFU; // Jump-immd[3:0]
59 1 : }
60 :
61 1 : void ConstructStore(const Rt91095StarsCondIsaRegister_t addrReg, const Rt91095StarsCondIsaRegister_t valReg,
62 : const uint16_t immdOffset, const Rt91095StarsCondIsaStoreFunc3_t func3, Rt91095StarsCondOpStore_t &opStore)
63 : {
64 1 : opStore.opCode = static_cast<uint32_t>(Rt91095StarsCondIsaOpCode_t::RT_91095_STARS_COND_ISA_OP_CODE_STORE);
65 1 : opStore.immdLow = static_cast<uint8_t>(immdOffset & 0x1FU); // S-immd[4:0]
66 1 : opStore.func3 = static_cast<uint32_t>(func3);
67 1 : opStore.rs1 = static_cast<uint32_t>(addrReg);
68 1 : opStore.rs2 = static_cast<uint32_t>(valReg);
69 1 : opStore.immdHigh = static_cast<uint8_t>((immdOffset & 0xFE0U) >> 5U); // S-immd[11:5]
70 1 : }
71 :
72 13 : void ConstructNop(Rt91095StarsCondOpNop_t &nop)
73 : {
74 13 : nop.opCode = static_cast<uint32_t>(Rt91095StarsCondIsaOpCode_t::RT_91095_STARS_COND_ISA_OP_CODE_NOP);
75 13 : nop.rd = static_cast<uint32_t>(Rt91095StarsCondIsaRegister_t::RT_91095_STARS_COND_ISA_REGISTER_R0);
76 13 : nop.func3 = static_cast<uint32_t>(Rt91095StarsCondIsaOpImmFunc3_t::RT_91095_STARS_COND_ISA_OP_IMM_FUNC3_NOP);
77 13 : nop.rs1 = static_cast<uint32_t>(Rt91095StarsCondIsaRegister_t::RT_91095_STARS_COND_ISA_REGISTER_R0);
78 13 : nop.immd = 0U;
79 13 : }
80 : }
81 :
82 1 : void BuildA5SqeCCoreNotifyWait(u32 streamId, u32 taskId, u64 waitAddr, u64 actAddr, bool last, uint8_t * const sqeIn)
83 : {
84 1 : Rt91095StarsCCoreSqeNotifyWait* sqe = (Rt91095StarsCCoreSqeNotifyWait *)sqeIn;
85 1 : sqe->header.type = static_cast<uint8_t>(Rt91095StarsSqeType::RT_91095_SQE_TYPE_COND);
86 1 : sqe->header.rtStreamId = static_cast<uint16_t>(taskId);
87 1 : sqe->header.taskId = static_cast<uint16_t>(taskId >> LOW_BITS);
88 :
89 1 : sqe->kernelCredit = RT_STARS_DEFAULT_KERNEL_CREDIT;
90 1 : sqe->csc = 1U;
91 :
92 1 : constexpr Rt91095StarsCondIsaRegister_t r0 = Rt91095StarsCondIsaRegister_t::RT_91095_STARS_COND_ISA_REGISTER_R0;
93 1 : constexpr Rt91095StarsCondIsaRegister_t r1 = Rt91095StarsCondIsaRegister_t::RT_91095_STARS_COND_ISA_REGISTER_R1;
94 1 : constexpr Rt91095StarsCondIsaRegister_t r2 = Rt91095StarsCondIsaRegister_t::RT_91095_STARS_COND_ISA_REGISTER_R2;
95 1 : constexpr Rt91095StarsCondIsaRegister_t r3 = Rt91095StarsCondIsaRegister_t::RT_91095_STARS_COND_ISA_REGISTER_R3;
96 :
97 : // load current Turn to r3
98 1 : ConstructLoadImm(r3, actAddr, Rt91095StarsCondIsaLoadImmFunc3_t::RT_91095_STARS_COND_ISA_LOAD_IMM_FUNC3_LHU, sqe->ldrImm1);
99 :
100 : // load sendcnt to r2
101 1 : ConstructLoadImm(r2, waitAddr, Rt91095StarsCondIsaLoadImmFunc3_t::RT_91095_STARS_COND_ISA_LOAD_IMM_FUNC3_LHU, sqe->ldrImm2);
102 1 : uint8_t loadInstrOff = (offsetof(Rt91095StarsCCoreSqeNotifyWait, ldrImm2) -
103 : offsetof(Rt91095StarsCCoreSqeNotifyWait, ldrImm1));
104 1 : loadInstrOff = loadInstrOff / sizeof(uint32_t);
105 :
106 : // r2(sendCnt) < r3(curTurn)，goto reload r2
107 1 : ConstructBranch(r2, r3, Rt91095StarsCondIsaBranchFunc3_t::RT_91095_STARS_COND_ISA_BRANCH_FUNC3_BLTU, loadInstrOff, sqe->beq);
108 :
109 1 : if (last) {
110 : // load sendcount addr to r1
111 0 : ConstructLLWI(r1, waitAddr, sqe->clear.llwi1);
112 0 : ConstructLHWI(r1, waitAddr, sqe->clear.lhwi1);
113 : // the last turn clear sendCnt, r0(0) value store to r1(sendCnt),
114 0 : ConstructStore(r1, r0, 0U, Rt91095StarsCondIsaStoreFunc3_t::RT_91095_STARS_COND_ISA_STORE_FUNC3_SH, sqe->clear.sw);
115 0 : for (Rt91095StarsCondOpNop_t &nop : sqe->clear.nop) {
116 0 : ConstructNop(nop);
117 : }
118 : } else {
119 8 : for (Rt91095StarsCondOpNop_t &nop : sqe->nop) {
120 7 : ConstructNop(nop);
121 : }
122 : }
123 :
124 3 : HCCL_INFO("[SQE]CCoreWait: waitAddr=%llu, actAddr=%llu, last=%u, streamId=%u, taskId=%u, "
125 : "ISA=%08x %08x %08x %08x %08x %08x %08x",
126 : waitAddr, actAddr, last, streamId, taskId,
127 : sqe->ldrImm1, sqe->ldrImm2, sqe->beq, sqe->clear.llwi1, sqe->clear.lhwi1, sqe->clear.sw, sqe->clear.nop[0]);
128 1 : }
129 :
130 1 : void BuildA5SqeCCoreNotifyRecord(u32 streamId, u32 taskId, u64 writeAddr, u64 valueAddr, uint8_t * const sqeIn)
131 : {
132 1 : Rt91095StarsCCoreSqeNotifyRecord* sqe = (Rt91095StarsCCoreSqeNotifyRecord *)sqeIn;
133 1 : sqe->header.type = static_cast<uint8_t>(Rt91095StarsSqeType::RT_91095_SQE_TYPE_COND);
134 1 : sqe->header.rtStreamId = static_cast<uint16_t>(taskId);
135 1 : sqe->header.taskId = static_cast<uint16_t>(taskId >> LOW_BITS);
136 :
137 1 : sqe->kernelCredit = RT_STARS_DEFAULT_KERNEL_CREDIT;
138 1 : sqe->csc = 1U;
139 :
140 1 : constexpr Rt91095StarsCondIsaRegister_t r1 = Rt91095StarsCondIsaRegister_t::RT_91095_STARS_COND_ISA_REGISTER_R1;
141 1 : constexpr Rt91095StarsCondIsaRegister_t r2 = Rt91095StarsCondIsaRegister_t::RT_91095_STARS_COND_ISA_REGISTER_R2;
142 :
143 1 : ConstructLoadImm(r1, valueAddr, Rt91095StarsCondIsaLoadImmFunc3_t::RT_91095_STARS_COND_ISA_LOAD_IMM_FUNC3_LHU, sqe->ldrImm);
144 1 : ConstructLLWI(r2, writeAddr, sqe->llwi1);
145 1 : ConstructLHWI(r2, writeAddr, sqe->lhwi1);
146 :
147 1 : ConstructStore(r2, r1, 0U, Rt91095StarsCondIsaStoreFunc3_t::RT_91095_STARS_COND_ISA_STORE_FUNC3_SH, sqe->sw);
148 7 : for (Rt91095StarsCondOpNop_t &nop : sqe->nop) {
149 6 : ConstructNop(nop);
150 : }
151 :
152 3 : HCCL_INFO("[SQE]CCoreWrite: writeAddr=%p, valueAddr=%p, streamId=%u, taskId=%u, "
153 : "ISA=%08x %08x %08x %08x %08x",
154 : writeAddr, valueAddr, streamId, taskId,
155 : sqe->ldrImm, sqe->llwi1, sqe->lhwi1, sqe->sw, sqe->nop[0]);
156 1 : }
157 :
158 : // 写64bit值的形式来完成敲DB
159 6 : void BuildA5SqeRdmaDbSend(u32 streamId, u32 taskId, u64 dbAddr, u64 dbValue, uint8_t * const sqeIn)
160 : {
161 : (void)streamId;
162 6 : Rt91095StarsWriteValueSqe *sqe = reinterpret_cast<Rt91095StarsWriteValueSqe *>(sqeIn);
163 6 : SetSqeHeaderTaskFields(sqe, taskId);
164 6 : sqe->header.type = static_cast<uint8_t>(Rt91095StarsSqeType::RT_91095_SQE_TYPE_WRITE_VALUE);
165 :
166 6 : sqe->kernelCredit = RT_STARS_DEFAULT_KERNEL_CREDIT;
167 6 : sqe->header.rtStreamId = streamId;
168 6 : sqe->header.taskId = taskId;
169 :
170 6 : sqe->writeAddrLow = dbAddr & MASK_32_BIT;
171 6 : sqe->writeAddrHigh = (dbAddr >> UINT32_BIT_NUM) & MASK_17_BIT;
172 :
173 6 : sqe->awsize = RtStarsWriteValueSizeType::RT_STARS_WRITE_VALUE_SIZE_TYPE_64BIT; // writeValue 为 8 byte
174 6 : sqe->writeValuePart[0] = static_cast<uint32_t>(dbValue & MASK_32_BIT); // low 32 bit
175 6 : sqe->writeValuePart[1] = static_cast<uint32_t>((dbValue >> UINT32_BIT_NUM) & MASK_32_BIT); // high 32 bit
176 :
177 6 : sqe->va = 1U;
178 6 : }
179 :
180 : } // namespace Hccl
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