Line data Source code
1 : /**
2 : * Copyright (c) 2025 Huawei Technologies Co., Ltd.
3 : * This program is free software, you can redistribute it and/or modify it under the terms and conditions of
4 : * CANN Open Software License Agreement Version 2.0 (the "License").
5 : * Please refer to the License for details. You may not use this file except in compliance with the License.
6 : * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR IMPLIED,
7 : * INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY, OR FITNESS FOR A PARTICULAR PURPOSE.
8 : * See LICENSE in the root of the software repository for the full text of the License.
9 : */
10 : #ifndef HCCLV2_RMA_CONN_LITE_H
11 : #define HCCLV2_RMA_CONN_LITE_H
12 : #include <memory>
13 : #include "rma_buf_slice_lite.h"
14 : #include "rmt_rma_buf_slice_lite.h"
15 : #include "log.h"
16 : #include "reduce_in.h"
17 : #include "data_type.h"
18 : #include "reduce_op.h"
19 : #include "ip_address.h"
20 : #include "ub_jetty_lite.h"
21 : #include "kernel_param_lite.h"
22 : #include "stream_lite.h"
23 : namespace Hccl {
24 : MAKE_ENUM(RmaConnLiteType, P2P, RDMA, UB, CCU) // 需要和RmaConnType一一对应
25 :
26 : struct SqeConfigLite {
27 39 : SqeConfigLite() : placeOdr(1), compOrder(1), fence(1) {}
28 : bool cqeEn{true};
29 : u8 placeOdr : 2;
30 : u8 compOrder : 1;
31 : u8 fence : 1;
32 : };
33 :
34 : struct ConnLiteOperationOut {
35 : u16 pi{0};
36 : u8 *data{};
37 : u8 dataSize{0};
38 : };
39 :
40 : class RmaConnLite {
41 : public:
42 53 : RmaConnLite() = default;
43 :
44 : RmaConnLite(const UbJettyLiteId &id, const UbJettyLiteAttr &attr, const Eid &rmtEid);
45 :
46 : explicit RmaConnLite(const u64 qpVa);
47 :
48 79 : virtual ~RmaConnLite() = default;
49 :
50 : static std::unique_ptr<RmaConnLite> Create(std::vector<char> &uniqueId);
51 :
52 : UbJettyLiteId GetUbJettyLiteId() const;
53 :
54 : UbJettyLiteAttr GetUbJettyLiteAttr() const;
55 :
56 : Eid GetRmtEid() const;
57 : Eid GetLocEid() const;
58 :
59 : u32 GetQpVa() const;
60 :
61 : virtual std::string Describe();
62 :
63 2 : virtual void Read(const RmaBufSliceLite &loc, const RmtRmaBufSliceLite &rmt, const SqeConfigLite &cfg,
64 : const StreamLite &stream, ConnLiteOperationOut &out)
65 : {
66 6 : HCCL_INFO("RmaConnLite read start. loc.addr = %llx, rmt.addr = %llx, cfg.cqeEn = %u, out.pi = %u",
67 : loc.GetAddr(), rmt.GetAddr(), cfg.cqeEn, out.pi);
68 2 : }
69 :
70 1 : virtual void ReadReduce(ReduceIn reduceIn, const RmaBufSliceLite &loc, const RmtRmaBufSliceLite &rmt,
71 : const StreamLite &stream, const SqeConfigLite &cfg, ConnLiteOperationOut &out)
72 : {
73 3 : HCCL_INFO("RmaConnLite ReadReduce start. dataType = %u, reduceOp %u, loc.addr = %llx, "
74 : "rmt.addr = %llx, cfg.cqeEn = %u, out.pi = %u",
75 : reduceIn.dataType, reduceIn.reduceOp, loc.GetAddr(), rmt.GetAddr(), cfg.cqeEn, out.pi);
76 1 : }
77 :
78 1 : virtual void Write(const RmaBufSliceLite &loc, const RmtRmaBufSliceLite &rmt, const SqeConfigLite &cfg,
79 : const StreamLite &stream, ConnLiteOperationOut &out)
80 : {
81 3 : HCCL_INFO("RmaConnLite write start. loc.addr = %llx, rmt.addr = %llx, cfg.cqeEn = %u, out.pi = %u",
82 : loc.GetAddr(), rmt.GetAddr(), cfg.cqeEn, out.pi);
83 1 : }
84 :
85 1 : virtual void InlineWrite(const u8 *data, u16 size, const RmtRmaBufSliceLite &rmt, const SqeConfigLite &cfg,
86 : const StreamLite &stream, ConnLiteOperationOut &out)
87 : {
88 3 : HCCL_INFO("RmaConnLite InlineWrite start. data = %p, size = %hu, rmt.addr = %llx, cfg.cqeEn = %u, out.pi = %u",
89 : data, size, rmt.GetAddr(), cfg.cqeEn, out.pi);
90 1 : }
91 :
92 1 : virtual void WriteReduce(DataType dataType, ReduceOp reduceOp, const RmaBufSliceLite &loc, const StreamLite &stream,
93 : const RmtRmaBufSliceLite &rmt, const SqeConfigLite &cfg, ConnLiteOperationOut &out)
94 : {
95 3 : HCCL_INFO("RmaConnLite WriteReduce start. dataType = %u, reduceOp %u, loc.addr = %llx, "
96 : "rmt.addr = %llx, cfg.cqeEn = %u, out.pi = %u",
97 : dataType, reduceOp, loc.GetAddr(), rmt.GetAddr(), cfg.cqeEn, out.pi);
98 1 : }
99 :
100 1 : virtual void WriteWithNotify(const RmaBufSliceLite &loc, const RmtRmaBufSliceLite &rmt, const SqeConfigLite &cfg,
101 : ConnLiteOperationOut &out, const RmtRmaBufSliceLite ¬ify, const StreamLite &stream,
102 : u64 notifyData)
103 : {
104 3 : HCCL_INFO("RmaConnLite WriteWithNotify start. loc.addr = %llx, rmt.addr = %llx, cfg.cqeEn = %u, "
105 : "out.pi = %u, notify.addr = %llx, notifyData = %u",
106 : loc.GetAddr(), rmt.GetAddr(), cfg.cqeEn, out.pi, notify.GetAddr(), notifyData);
107 1 : }
108 :
109 0 : virtual void WriteReduceWithNotify(DataType dataType, ReduceOp reduceOp, const RmaBufSliceLite &loc,
110 : const RmtRmaBufSliceLite &rmt, const SqeConfigLite &cfg, const StreamLite &stream,
111 : ConnLiteOperationOut &out, const RmtRmaBufSliceLite ¬ify, u64 notifyData)
112 : {
113 0 : HCCL_INFO("RmaConnLite WriteReduceWithNotify start. dataType = %d, , reduceOp %d, loc.addr = %llx, "
114 : "rmt.addr = %llx, cfg.cqeEn = %u, out.pi = %u, notify.addr = %llx, notifyData = %llu",
115 : dataType, reduceOp, loc.GetAddr(), rmt.GetAddr(), cfg.cqeEn, out.pi, notify.GetAddr(), notifyData);
116 0 : }
117 :
118 1 : virtual void BatchOneSidedRead(const vector<RmaBufSliceLite> &loc, const vector<RmtRmaBufSliceLite> &rmt, const SqeConfigLite &cfg,
119 : const StreamLite &stream, ConnLiteOperationOut &out)
120 : {
121 3 : HCCL_INFO("RmaConnLite BatchOneSidedRead start. loc.size = %llu, rmt.size = %llu, cfg.cqeEn = %u, out.pi = %u",
122 : loc.size(), rmt.size(), cfg.cqeEn, out.pi);
123 1 : }
124 :
125 1 : virtual void BatchOneSidedWrite(const vector<RmaBufSliceLite> &loc, const vector<RmtRmaBufSliceLite> &rmt, const SqeConfigLite &cfg,
126 : const StreamLite &stream, ConnLiteOperationOut &out)
127 : {
128 3 : HCCL_INFO("RmaConnLite BatchOneSidedWrite start. loc.size = %llu, rmt.size = %llu, cfg.cqeEn = %u, out.pi = %u",
129 : loc.size(), rmt.size(), cfg.cqeEn, out.pi);
130 1 : }
131 :
132 : protected:
133 : u32 qpVa_{0};
134 :
135 : u32 dieId_{0};
136 : u32 funcId_{0};
137 : u32 jettyId_{0};
138 : u64 dbAddr_{0};
139 : u64 sqVa_{0};
140 : u32 sqDepth_{0};
141 : bool dwqeCacheLocked_{false}; // direct WQE cache Lock
142 : u32 jfcPollMode_{0}; // 0代表STARS POLL， 1代表软件Poll
143 : u32 tpn_{0};
144 :
145 : Eid rmtEid_;
146 : Eid locEid_;
147 : };
148 :
149 : } // namespace Hccl
150 : #endif
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