Line data Source code
1 : /**
2 : * Copyright (c) 2025 Huawei Technologies Co., Ltd.
3 : * This program is free software, you can redistribute it and/or modify it under the terms and conditions of
4 : * CANN Open Software License Agreement Version 2.0 (the "License").
5 : * Please refer to the License for details. You may not use this file except in compliance with the License.
6 : * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR IMPLIED,
7 : * INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY, OR FITNESS FOR A PARTICULAR PURPOSE.
8 : * See LICENSE in the root of the software repository for the full text of the License.
9 : */
10 :
11 : #include "aicpu/aicpu_hccl_sqcq.h"
12 : #include "adapter_hal_pub.h"
13 : #include "sal_pub.h"
14 : #include "hcomm_task_struct.h"
15 : #include "common/type_def.h"
16 :
17 : using char_t = char;
18 :
19 : extern "C" {
20 : drvError_t __attribute__((weak)) halCqReportRecv(uint32_t devId, struct halReportRecvInfo *info);
21 : drvError_t __attribute__((weak)) halSqCqQuery(uint32_t devId, struct halSqCqQueryInfo *info);
22 : drvError_t __attribute__((weak)) halSqCqConfig(uint32_t devId, struct halSqCqConfigInfo *info);
23 : drvError_t __attribute__((weak)) halTsdrvCtl(uint32_t devId, int cmd, void *param, size_t paramSize, void *out, size_t *outSize);
24 : drvError_t __attribute__((weak)) halEschedSubmitEvent(uint32_t devId, struct event_summary *event);
25 : };
26 :
27 1104 : HcclResult QuerySqBaseAddr(uint32_t devId, uint32_t sqId, u64 &outVal)
28 : {
29 1104 : CHK_PRT_RET((halSqCqQuery == nullptr), HCCL_ERROR("halSqCqQuery is nullptr, "
30 : "Does not support this interface."), HCCL_E_DRV);
31 : halSqCqQueryInfo queryinfo;
32 1104 : queryinfo.tsId = 0;
33 1104 : queryinfo.sqId = sqId;
34 1104 : queryinfo.cqId = 0;
35 1104 : queryinfo.type = DRV_NORMAL_TYPE;
36 :
37 1104 : queryinfo.prop = DRV_SQCQ_PROP_SQ_BASE;
38 1104 : uint32_t ret = halSqCqQuery(devId, &queryinfo);
39 1104 : if (ret != 0) {
40 1 : HCCL_ERROR("halSqCqQuery base addr failed. ret = %d sqid:%d\n", ret, queryinfo.sqId);
41 1 : return HCCL_E_DRV;
42 : }
43 :
44 1103 : outVal = ((static_cast<u64>(queryinfo.value[1])) << UINT32_BIT_NUM) | queryinfo.value[0];
45 :
46 1103 : HCCL_DEBUG("valu1:%x. value0:%x, outValue:%p", queryinfo.value[1], queryinfo.value[0], outVal);
47 :
48 1103 : return HCCL_SUCCESS;
49 : }
50 :
51 797 : HcclResult QuerySqStatusByType(uint32_t devId, uint32_t sqId, drvSqCqPropType_t type, uint32_t &outVal)
52 : {
53 797 : CHK_PRT_RET((halSqCqQuery == nullptr), HCCL_ERROR("halSqCqQuery is nullptr, "
54 : "Does not support this interface."), HCCL_E_DRV);
55 : halSqCqQueryInfo queryinfo;
56 797 : queryinfo.tsId = 0;
57 797 : queryinfo.sqId = sqId;
58 797 : queryinfo.cqId = 0;
59 797 : queryinfo.type = DRV_NORMAL_TYPE;
60 :
61 797 : queryinfo.prop = type;
62 797 : uint32_t ret = halSqCqQuery(devId, &queryinfo);
63 797 : if (ret != 0) {
64 2 : HCCL_ERROR("halSqCqQuery %d failed. ret = %d sqid:%d\n", type, ret, queryinfo.sqId);
65 2 : return HCCL_E_DRV;
66 : }
67 795 : outVal = queryinfo.value[0];
68 :
69 795 : return HCCL_SUCCESS;
70 : }
71 :
72 68 : HcclResult QuerySqStatus(uint32_t devId, uint32_t sqId, uint32_t &sqHead, uint32_t &sqTail)
73 : {
74 68 : HcclResult ret = QuerySqStatusByType(devId, sqId, DRV_SQCQ_PROP_SQ_TAIL, sqTail);
75 68 : if (ret != 0) {
76 1 : HCCL_ERROR(" halSqCqQuery TAIL failed. ret = %d sqid:%d\n", ret, sqId);
77 1 : return ret;
78 : }
79 :
80 67 : ret = QuerySqStatusByType(devId, sqId, DRV_SQCQ_PROP_SQ_HEAD, sqHead);
81 67 : if (ret != 0) {
82 0 : HCCL_ERROR(" halSqCqQuery HEAD failed. ret = %d sqid:%d\n", ret, sqId);
83 0 : return ret;
84 : }
85 :
86 67 : return ret;
87 : }
88 :
89 651 : HcclResult ConfigSqStatusByType(uint32_t devId, uint32_t sqId, drvSqCqPropType_t type, uint32_t value)
90 : {
91 651 : CHK_PRT_RET((halSqCqConfig == nullptr), HCCL_ERROR("halSqCqConfig is nullptr, "
92 : "Does not support this interface."), HCCL_E_DRV);
93 : halSqCqConfigInfo configInfo;
94 651 : configInfo.tsId = 0;
95 651 : configInfo.sqId = sqId;
96 651 : configInfo.cqId = 0;
97 651 : configInfo.type = DRV_NORMAL_TYPE;
98 :
99 651 : configInfo.prop = type;
100 651 : configInfo.value[0] = value;
101 651 : uint32_t ret = halSqCqConfig(devId, &configInfo);
102 651 : if (ret != 0) {
103 1 : HCCL_ERROR("halSqCqConfig %d failed. ret = %d sqid:%d, type:%d, value:%d", type, ret, configInfo.sqId,
104 : type, value);
105 1 : return HCCL_E_DRV;
106 : }
107 650 : return HCCL_SUCCESS;
108 : }
109 :
110 : namespace {
111 229 : void ConstructLHWI(const rtStarsCondIsaRegister_t dstReg, const u64 immd, rtStarsCondOpLHWI_t &opLHWI)
112 : {
113 229 : opLHWI.opCode = RT_STARS_COND_ISA_OP_CODE_LWI;
114 229 : opLHWI.func3 = RT_STARS_COND_ISA_LWI_FUNC3_LHWI;
115 229 : opLHWI.rd = dstReg;
116 229 : opLHWI.immd = static_cast<uint32_t>((immd >> 49U) & 0x7FFFU); // High15-immd[63:49]
117 229 : }
118 :
119 229 : void ConstructLLWI(const rtStarsCondIsaRegister_t dstReg, const u64 immd, rtStarsCondOpLLWI_t &opLLWI)
120 : {
121 229 : opLLWI.opCode = RT_STARS_COND_ISA_OP_CODE_LWI;
122 229 : opLLWI.func3 = RT_STARS_COND_ISA_LWI_FUNC3_LLWI;
123 229 : opLLWI.rd = dstReg;
124 229 : opLLWI.immdHigh = static_cast<uint32_t>((immd >> 32U) & 0x1FFFFU); // Low49-immd[48:32]
125 229 : opLLWI.immdLow = static_cast<uint32_t>(immd & 0xFFFFFFFFU); // Low49-immd[31:0]
126 229 : }
127 :
128 517 : void ConstructLoadImm(const rtStarsCondIsaRegister_t dstReg, const u64 addr,
129 : const rtStarsCondIsaLoadImmFunc3_t func3, rtStarsCondOpLoadImm_t &loadImm)
130 : {
131 517 : loadImm.opCode = RT_STARS_COND_ISA_OP_CODE_LOAD_IMM;
132 517 : loadImm.rd = dstReg;
133 517 : loadImm.func3 = func3;
134 517 : loadImm.immdAddrHigh = static_cast<uint32_t>((addr >> 32U) & 0X1FFFFU); // bit[48:32]
135 517 : loadImm.immdAddrLow = static_cast<uint32_t>(addr & 0xFFFFFFFFU); // bit[31:0]
136 517 : }
137 :
138 174 : void ConstructBranch(const rtStarsCondIsaRegister_t rs1Reg, const rtStarsCondIsaRegister_t rs2Reg,
139 : const rtStarsCondIsaBranchFunc3_t func3, const uint8_t instrOffset,
140 : rtStarsCondOpBranch_t &opBranch)
141 : {
142 174 : opBranch.opCode = RT_STARS_COND_ISA_OP_CODE_BRANCH;
143 174 : opBranch.func3 = func3;
144 174 : opBranch.rs1 = rs1Reg;
145 174 : opBranch.rs2 = rs2Reg;
146 174 : opBranch.jumpInstrOffset = instrOffset & 0xFU; // Jump-immd[3:0]
147 174 : }
148 :
149 229 : void ConstructStore(const rtStarsCondIsaRegister_t addrReg, const rtStarsCondIsaRegister_t valReg,
150 : const uint16_t immdOffset, const rtStarsCondIsaStoreFunc3_t func3, rtStarsCondOpStore_t &opStore)
151 : {
152 229 : opStore.opCode = RT_STARS_COND_ISA_OP_CODE_STORE;
153 229 : opStore.immdLow = static_cast<uint8_t>(immdOffset & 0x1FU); // S-immd[4:0]
154 229 : opStore.func3 = func3;
155 229 : opStore.rs1 = addrReg;
156 229 : opStore.rs2 = valReg;
157 229 : opStore.immdHigh = static_cast<uint8_t>((immdOffset & 0xFE0U) >> 5U); // S-immd[11:5]
158 229 : }
159 :
160 1992 : void ConstructNop(rtStarsCondOpNop_t &nop)
161 : {
162 1992 : nop.opCode = RT_STARS_COND_ISA_OP_CODE_NOP;
163 1992 : nop.rd = RT_STARS_COND_ISA_REGISTER_R0;
164 1992 : nop.func3 = RT_STARS_COND_ISA_OP_IMM_FUNC3_NOP;
165 1992 : nop.rs1 = RT_STARS_COND_ISA_REGISTER_R0;
166 1992 : nop.immd = 0U;
167 1992 : }
168 : } // namespace
169 :
170 174 : void AddOneWaitStartSqe(uint16_t streamId, uint16_t taskId, u64 waitAddr, u64 curTurnCntAddr, bool last,
171 : rtStarsCcoreWaitStartSqe_t *const sqe, uint8_t *sqeType)
172 : {
173 174 : *sqeType = SqeType::CCORE_WAIT_START_SQE;
174 174 : sqe->sqeHeader.type = RT_STARS_SQE_TYPE_COND;
175 174 : sqe->sqeHeader.rtStreamId = streamId;
176 174 : sqe->sqeHeader.taskId = taskId;
177 :
178 174 : sqe->kernel_credit = RT_STARS_DEFAULT_KERNEL_CREDIT;
179 174 : sqe->csc = 1U;
180 :
181 174 : constexpr rtStarsCondIsaRegister_t r0 = RT_STARS_COND_ISA_REGISTER_R0;
182 174 : constexpr rtStarsCondIsaRegister_t r1 = RT_STARS_COND_ISA_REGISTER_R1;
183 174 : constexpr rtStarsCondIsaRegister_t r2 = RT_STARS_COND_ISA_REGISTER_R2;
184 174 : constexpr rtStarsCondIsaRegister_t r3 = RT_STARS_COND_ISA_REGISTER_R3;
185 :
186 : // load current Turn to r3
187 174 : ConstructLoadImm(r3, curTurnCntAddr, RT_STARS_COND_ISA_LOAD_IMM_FUNC3_LHU, sqe->ldrImm1);
188 :
189 : // load sendcnt to r2
190 174 : ConstructLoadImm(r2, waitAddr, RT_STARS_COND_ISA_LOAD_IMM_FUNC3_LHU, sqe->ldrImm2);
191 174 : uint8_t loadInstrOff = (offsetof(rtStarsCcoreWaitStartSqe_t, ldrImm2) -
192 : offsetof(rtStarsCcoreWaitStartSqe_t, ldrImm1));
193 174 : loadInstrOff = loadInstrOff / sizeof(uint32_t);
194 :
195 : // r2(sendCnt) < r3(curTurn)，goto reload r2
196 174 : ConstructBranch(r2, r3, RT_STARS_COND_ISA_BRANCH_FUNC3_BLTU, loadInstrOff, sqe->beq);
197 :
198 174 : if (last) {
199 : // load sendcount addr to r1
200 60 : ConstructLLWI(r1, waitAddr, sqe->clear.llwi1);
201 60 : ConstructLHWI(r1, waitAddr, sqe->clear.lhwi1);
202 : // the last turn clear sendCnt, r0(0) value store to r1(sendCnt),
203 60 : ConstructStore(r1, r0, 0U, RT_STARS_COND_ISA_STORE_FUNC3_SH, sqe->clear.sw);
204 240 : for (rtStarsCondOpNop_t &nop : sqe->clear.nop) {
205 180 : ConstructNop(nop);
206 : }
207 : } else {
208 912 : for (rtStarsCondOpNop_t &nop : sqe->nop) {
209 798 : ConstructNop(nop);
210 : }
211 : }
212 :
213 174 : HCCL_INFO("WaitStart waitAddr %p, curTurnCntAddr %p, loadInstrOff %u, streamId %u, taskId %u, last %u"
214 : "ISA: %08x %08x %08x %08x %08x %08x %08x.",
215 : waitAddr, curTurnCntAddr, loadInstrOff, streamId, taskId, last,
216 : sqe->ldrImm1, sqe->ldrImm2, sqe->beq, sqe->clear.llwi1, sqe->clear.lhwi1, sqe->clear.sw, sqe->clear.nop[0]);
217 174 : }
218 :
219 169 : void AddOneWriteValueStartSqe(uint16_t streamId, uint16_t taskId, u64 writeAddr, u64 valueAddr,
220 : rtStarsCcoreWriteValueSqe_t *const sqe, uint8_t *sqeType)
221 : {
222 169 : *sqeType = SqeType::CCORE_WRITE_VALUE_SQE;
223 169 : sqe->sqeHeader.type = RT_STARS_SQE_TYPE_COND;
224 169 : sqe->sqeHeader.rtStreamId = streamId;
225 169 : sqe->sqeHeader.taskId = taskId;
226 :
227 169 : sqe->kernel_credit = RT_STARS_DEFAULT_KERNEL_CREDIT;
228 169 : sqe->csc = 1U;
229 :
230 169 : constexpr rtStarsCondIsaRegister_t r1 = RT_STARS_COND_ISA_REGISTER_R1;
231 169 : constexpr rtStarsCondIsaRegister_t r2 = RT_STARS_COND_ISA_REGISTER_R2;
232 :
233 169 : ConstructLoadImm(r1, valueAddr, RT_STARS_COND_ISA_LOAD_IMM_FUNC3_LHU, sqe->ldrImm);
234 169 : ConstructLLWI(r2, writeAddr, sqe->llwi1);
235 169 : ConstructLHWI(r2, writeAddr, sqe->lhwi1);
236 :
237 169 : ConstructStore(r2, r1, 0U, RT_STARS_COND_ISA_STORE_FUNC3_SH, sqe->sw);
238 1183 : for (rtStarsCondOpNop_t &nop : sqe->nop) {
239 1014 : ConstructNop(nop);
240 : }
241 :
242 169 : HCCL_INFO("CCore write value: writeAddr %p, valueAddr %p, streamId %u, taskId %u"
243 : "ISA: %08x %08x %08x %08x %08x.",
244 : writeAddr, valueAddr, streamId, taskId,
245 : sqe->ldrImm, sqe->llwi1, sqe->lhwi1, sqe->sw, sqe->nop[0]);
246 169 : }
247 :
248 16 : std::string StringLogicCqReportInfo(const rtLogicCqReport_t &reportOfOne)
249 : {
250 16 : std::stringstream ss;
251 16 : ss << "streamId :" << reportOfOne.streamId;
252 16 : ss << " taskId :" << reportOfOne.taskId;
253 16 : ss << " errorCode :" << reportOfOne.errorCode;
254 16 : ss << " errorType :" << static_cast<uint32_t>(reportOfOne.errorType);
255 16 : ss << " sqeType :" << static_cast<uint32_t>(reportOfOne.sqeType);
256 16 : ss << " sqId :" << reportOfOne.sqId;
257 16 : ss << " sqHead :" << reportOfOne.sqHead;
258 16 : ss << " matchFlag :" << reportOfOne.matchFlag;
259 16 : ss << " dropFlag :" << reportOfOne.dropFlag;
260 16 : ss << " errorBit :" << reportOfOne.errorBit;
261 16 : ss << " accError :" << reportOfOne.accError;
262 32 : return ss.str();
263 16 : }
264 :
265 8 : bool IsExceptionCqe(const rtLogicCqReport_t &reportOfOne)
266 : {
267 8 : HCCL_DEBUG("ReportOfOne info [%s]", StringLogicCqReportInfo(reportOfOne).c_str());
268 8 : if ((reportOfOne.errorType & RT_STARS_EXIST_ERROR) == 0U) { // 取低5位
269 0 : return false;
270 : }
271 8 : return true;
272 : }
273 :
274 :
275 18 : CqeStatus CqReportRecv(const CqeQueryInput &cqeQueryInput, rtLogicCqReport_t &cqeException)
276 : {
277 18 : CHK_PRT_RET((halCqReportRecv == nullptr), HCCL_ERROR("halCqReportRecv is nullptr, "
278 : "Does not support this interface."), CqeStatus::kCqeInnerError);
279 : halReportRecvInfo recvInfo;
280 18 : recvInfo.type = static_cast<drvSqCqType_t>(cqeQueryInput.type);
281 18 : recvInfo.tsId = 0;
282 18 : recvInfo.report_cqe_num = 0;
283 18 : recvInfo.stream_id = cqeQueryInput.streamId;
284 18 : recvInfo.cqId = cqeQueryInput.cqId;
285 18 : recvInfo.timeout = 0; // 不设置超时时间，非阻塞
286 18 : recvInfo.task_id = 0xFFFF; // 接收所有类型
287 18 : recvInfo.cqe_addr = cqeQueryInput.cqeAddr; // 外部保证是有效的地址
288 18 : recvInfo.cqe_num = (recvInfo.type == DRV_LOGIC_TYPE ? AC_SQE_REV_MAX_CNT : MAX_REPORT_CNT);
289 18 : drvError_t ret = halCqReportRecv(cqeQueryInput.devId, &recvInfo);
290 18 : if (ret == DRV_ERROR_WAIT_TIMEOUT) {
291 1 : HCCL_DEBUG("halCqReportRecv has found nothing, ret:%d", ret);
292 1 : return CqeStatus::kCqeTimeOut;
293 : }
294 17 : if (ret != DRV_ERROR_NONE) {
295 1 : HCCL_ERROR("halCqReportRecv failed, ret:%d", ret);
296 1 : return CqeStatus::kCqeInnerError;
297 : }
298 16 : if (recvInfo.type != DRV_LOGIC_TYPE) { // 非DRV_LOGIC_TYPE不支持解析
299 0 : return CqeStatus::kDefault;
300 : }
301 16 : uint32_t reportNum = recvInfo.report_cqe_num;
302 16 : CHK_PRT_RET(reportNum > AC_SQE_REV_MAX_CNT, HCCL_ERROR("report cqe num %u should "
303 : "not big than %u",
304 : reportNum,
305 : AC_SQE_REV_MAX_CNT), CqeStatus::kCqeUnknown);
306 16 : for (uint32_t idx = 0U; idx < reportNum; ++idx) {
307 8 : const auto &reportOfOne =
308 8 : *((reinterpret_cast<rtLogicCqReport_t *>(recvInfo.cqe_addr)) + idx); // 外部保证是有效的地址
309 8 : if (IsExceptionCqe(reportOfOne)) {
310 8 : HCCL_ERROR("Task {%s} run failed of exception, idx:[%u], info:[%s]",
311 : cqeQueryInput.ToString().c_str(),
312 : idx,
313 : StringLogicCqReportInfo(reportOfOne).c_str());
314 8 : cqeException = reportOfOne;
315 8 : return CqeStatus::kCqeException;
316 : }
317 : }
318 8 : return CqeStatus::kDefault;
319 : }
320 :
321 4 : HcclResult StreamsKill(const uint32_t devId)
322 : {
323 4 : CHK_PRT_RET((halTsdrvCtl == nullptr), HCCL_ERROR("halTsdrvCtl is nullptr, "
324 : "Does not support this interface."), HCCL_E_DRV);
325 4 : ts_ctrl_msg_body_t killIn = {};
326 4 : ts_ctrl_msg_body_t killAck = {};
327 4 : size_t ackCount = sizeof(ts_ctrl_msg_body_t);
328 4 : killIn.type = OP_ABORT_APP;
329 4 : struct tsdrv_ctrl_msg para = {};
330 4 : para.tsid = 0;
331 4 : para.msg_len = sizeof(ts_ctrl_msg_body_t);
332 4 : para.msg = static_cast<void*>(&killIn);
333 4 : const drvError_t ret = halTsdrvCtl(devId, TSDRV_CTL_CMD_CTRL_MSG,
334 : static_cast<void*>(¶), sizeof(tsdrv_ctrl_msg), static_cast<void*>(&killAck), &ackCount);
335 4 : if (ret != DRV_ERROR_NONE) {
336 2 : HCCL_ERROR("halTsdrvCtl failed. ret = %d\n", ret);
337 2 : return HCCL_E_DRV;
338 : }
339 2 : return HCCL_SUCCESS;
340 : }
341 :
342 3 : inline u64 GetCurCpuTimestamp()
343 : {
344 3 : constexpr u64 NSEC_PER_SEC = 1000000000U;
345 : struct timespec timestamp;
346 3 : (void)clock_gettime(CLOCK_MONOTONIC_RAW, ×tamp);
347 3 : return static_cast<u64>((timestamp.tv_sec * NSEC_PER_SEC) + (timestamp.tv_nsec));
348 : }
349 :
350 3 : HcclResult DeviceQuery(const uint32_t devId, const uint32_t step, const uint32_t timeout)
351 : {
352 3 : CHK_PRT_RET((halTsdrvCtl == nullptr), HCCL_ERROR("halTsdrvCtl is nullptr, "
353 : "Does not support this interface."), HCCL_E_DRV);
354 : uint32_t status;
355 : uint64_t endTime;
356 3 : const uint64_t startTime = GetCurCpuTimestamp();
357 3 : bool flag = true;
358 3 : while (flag) {
359 3 : ts_ctrl_msg_body_t queryIn = {};
360 3 : ts_ctrl_msg_body_t queryAck = {};
361 3 : size_t ackCount = sizeof(ts_ctrl_msg_body_t);
362 3 : queryIn.type = OP_QUERY_ABORT_STATUS;
363 3 : queryIn.u.query_task_info.choice = APP_ABORT_STS_QUERY_BY_PID;
364 3 : struct tsdrv_ctrl_msg para = {};
365 3 : para.tsid = 0;
366 3 : para.msg_len = sizeof(ts_ctrl_msg_body_t);
367 3 : para.msg = static_cast<void*>(&queryIn);
368 3 : const drvError_t ret = halTsdrvCtl(devId, TSDRV_CTL_CMD_CTRL_MSG,
369 : static_cast<void*>(¶), sizeof(tsdrv_ctrl_msg), static_cast<void*>(&queryAck), &ackCount);
370 3 : if ((ret != DRV_ERROR_NONE) || (ackCount != sizeof(ts_ctrl_msg_body_t))) {
371 1 : HCCL_ERROR("halTsdrvCtl failed. ret = %d\n", ret);
372 1 : return HCCL_E_DRV;
373 : }
374 :
375 2 : status = queryAck.u.query_task_ack_info.status;
376 2 : if (status >= step) {
377 2 : flag = false;
378 2 : break;
379 : }
380 0 : endTime = GetCurCpuTimestamp();
381 0 : if ((timeout != 0U) && ((endTime - startTime) > timeout)) {
382 0 : HCCL_ERROR("kill query timeout.\n");
383 0 : return HCCL_E_TIMEOUT;
384 : }
385 0 : SaluSleep(5000U);
386 : }
387 2 : return HCCL_SUCCESS;
388 : }
389 :
390 : namespace hccl_plf {
391 : // 把SDMA类错误码转换成Ts对应的错误码
392 0 : uint16_t SwitchSdmaCqeErrCodeToTsErrCode(u32 cqeErrCode){
393 0 : switch (cqeErrCode) {
394 0 : case RT_SDMA_COMPERR:
395 0 : return TS_ERROR_SDMA_LINK_ERROR;
396 0 : case RT_SDMA_COMPDATAERR:
397 0 : return TS_ERROR_SDMA_POISON_ERROR;
398 0 : case RT_SDMA_DATAERR:
399 0 : return TS_ERROR_SDMA_DDRC_ERROR;
400 0 : case TS_ERROR_RETRY_CONSTRAINT:
401 0 : return TS_ERROR_RETRY_CONSTRAINT;
402 0 : default:
403 0 : return TS_ERROR_HCCL_OTHER_ERROR;
404 : }
405 : }
406 :
407 0 : HcclResult SendTaskExceptionByMBox(const u32 localDeviceId, const u32 notifyId, const u32 tsId,
408 : const s32 userStreamId, const u32 cqeErrCode)
409 : {
410 0 : CHK_PRT_RET((halEschedSubmitEvent == nullptr), HCCL_ERROR("halEschedSubmitEvent is nullptr, "
411 : "Does not support this interface."), HCCL_E_DRV);
412 0 : ts_aicpu_sqe_t aicpuSqe = {};
413 0 : u32 hostpid = 0;
414 0 : u32 vf_id = 0;
415 : // 调整drvQueryProcessHostPid获取pid和vf_id的值
416 0 : CHK_RET(HrtHalDrvQueryProcessHostPid(getpid(), nullptr, &vf_id, &hostpid, nullptr));
417 :
418 0 : aicpuSqe.pid = hostpid;
419 0 : aicpuSqe.cmd_type = AICPU_RECORD;
420 0 : aicpuSqe.vf_id = vf_id;
421 0 : aicpuSqe.tid = 0U; // notify is no need tid
422 0 : aicpuSqe.u.aicpu_record.record_type = AICPU_MSG_NOTIFY_RECORD;
423 0 : aicpuSqe.u.aicpu_record.record_id = notifyId;
424 :
425 0 : aicpuSqe.ts_id = static_cast<uint8_t>(tsId);
426 :
427 0 : aicpuSqe.u.aicpu_record.fault_stream_id = static_cast<uint16_t>(userStreamId);
428 :
429 0 : aicpuSqe.u.aicpu_record.ret_code = SwitchSdmaCqeErrCodeToTsErrCode(cqeErrCode);
430 :
431 0 : struct event_summary event = {};
432 0 : event.dst_engine = TS_CPU;
433 0 : event.policy = ONLY;
434 0 : event.pid = 0;
435 0 : event.grp_id = 0;
436 0 : event.event_id = EVENT_TS_CTRL_MSG;
437 0 : event.subevent_id = 0U;
438 0 : event.msg_len = static_cast<uint32_t>(sizeof(ts_aicpu_sqe_t));
439 0 : event.msg = PtrToPtr<ts_aicpu_sqe_t, char_t>(&aicpuSqe);
440 0 : auto ret = halEschedSubmitEvent(localDeviceId, &event);
441 0 : if (ret != static_cast<int32_t>(DRV_ERROR_NONE)) {
442 0 : HCCL_ERROR("[SendTaskExceptionByMBox]Send msg async to ts failed. ret=%d, streamId=%d, "
443 : "notifyId=%u.", ret, userStreamId, notifyId);
444 0 : return HCCL_E_DRV;
445 : }
446 0 : HCCL_RUN_INFO("[SendTaskExceptionByMBox]Send msg async to ts finished. streamId=%d, notifyId=%u, msg_size=%u, "
447 : "hostpid=%u, vf_id=%u, errCode=%u.", userStreamId, notifyId,
448 : static_cast<uint32_t>(sizeof(ts_aicpu_sqe_t)), hostpid, vf_id, cqeErrCode);
449 0 : return HCCL_SUCCESS;
450 : }
451 : } // namespace hccl_plf
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