Line data Source code
1 : /**
2 : * Copyright (c) 2025 Huawei Technologies Co., Ltd.
3 : * This program is free software, you can redistribute it and/or modify it under the terms and conditions of
4 : * CANN Open Software License Agreement Version 2.0 (the "License").
5 : * Please refer to the License for details. You may not use this file except in compliance with the License.
6 : * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR IMPLIED,
7 : * INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY, OR FITNESS FOR A PARTICULAR PURPOSE.
8 : * See LICENSE in the root of the software repository for the full text of the License.
9 : */
10 :
11 : #include "coll_all_to_all_v_fullmesh_executor.h"
12 :
13 : namespace hccl {
14 :
15 0 : CollRunAlltoAllVFullMesh::CollRunAlltoAllVFullMesh(const HcclDispatcher dispatcher,
16 0 : std::unique_ptr<TopoMatcher> &topoMatcher)
17 0 : : CollAlltoAllExecutor(dispatcher, topoMatcher)
18 : {
19 0 : }
20 :
21 0 : HcclResult CollRunAlltoAllVFullMesh::CalcStreamNum(u32& streamNum)
22 : {
23 0 : if (SatisfyIntraSuperPod(topoAttr_.deviceType, topoAttr_.userRankSize, topoAttr_.useSuperPodMode,
24 0 : topoAttr_.superPodNum)) {
25 0 : streamNum = topoAttr_.userRankSize - 1;
26 : } else {
27 0 : streamNum = 0;
28 : }
29 0 : HCCL_INFO("[CollRunAlltoAllVFullMesh][CalcStreamNum] tag[%s] streamNum[%u]",
30 : tag_.c_str(), streamNum);
31 0 : return HCCL_SUCCESS;
32 : }
33 :
34 : // level0-level1 打平fullmesh
35 0 : HcclResult CollRunAlltoAllVFullMesh::CalcLevel0CommInfo(TransportMemType inputType, TransportMemType outputType,
36 : std::vector<LevelNSubCommTransport>& opTransport)
37 : {
38 0 : CommParaInfo commCombinePara(COMM_COMBINE_ORDER, CommType::COMM_TAG_MESH);
39 0 : CHK_RET(CalcCommPlaneInfo(tag_, commCombinePara, opTransport[COMM_COMBINE_ORDER], inputType, outputType));
40 0 : return HCCL_SUCCESS;
41 0 : }
42 :
43 0 : HcclResult CollRunAlltoAllVFullMesh::CalcLevel2CommInfo(TransportMemType inputType,
44 : TransportMemType outputType,
45 : std::vector<LevelNSubCommTransport>& opTransport)
46 : {
47 0 : CommParaInfo commParaLevel2(COMM_LEVEL2, CommType::COMM_TAG_MESH);
48 0 : CHK_RET(CalcCommPlaneInfo(tag_, commParaLevel2, opTransport[COMM_LEVEL2], inputType, outputType));
49 0 : return HCCL_SUCCESS;
50 0 : }
51 :
52 :
53 0 : HcclResult CollRunAlltoAllVFullMesh::CalAlltoAllFullMeshCommInfo(TransportMemType inputType,
54 : TransportMemType outputType,
55 : std::vector<LevelNSubCommTransport>& opTransport)
56 : {
57 : (void) inputType;
58 : (void) outputType;
59 : // A+X单机双module启用下，未使能RDMA不能进行一层pairWise。
60 0 : bool isDifModule = topoAttr_.serverNum == 1 && topoAttr_.isDiffDeviceModule &&
61 0 : topoAttr_.userRankSize > HCCL_ALLTOALLV_P2P_SIZE;
62 0 : CHK_PRT_RET(isDifModule && !algoAttr_.isUsedRdmaLevel0,
63 : HCCL_ERROR("[CalAlltoAllFullMeshCommInfo] not support dual modules in a single server" \
64 : " when RDMA disabled "), HCCL_E_NOT_SUPPORT);
65 :
66 : // 将网卡初始化判断，提到上层调用，减少无必要的循环依赖。
67 0 : if (workflowMode_ == HcclWorkflowMode::HCCL_WORKFLOW_MODE_OP_BASE) {
68 : // level0 - level1 全连接通信域
69 0 : CHK_RET(CalcLevel0CommInfo(TransportMemType::CCL_INPUT, TransportMemType::CCL_OUTPUT, opTransport));
70 : // level2 层通信域
71 0 : CHK_RET(CalcLevel2CommInfo(TransportMemType::CCL_INPUT, TransportMemType::CCL_OUTPUT, opTransport));
72 : } else {
73 : // level0 - level1 全连接通信域
74 0 : CHK_RET(CalcLevel0CommInfo(TransportMemType::PARAM_INPUT, TransportMemType::PARAM_OUTPUT, opTransport));
75 : // level2 层通信域
76 0 : CHK_RET(CalcLevel2CommInfo(TransportMemType::PARAM_INPUT, TransportMemType::PARAM_OUTPUT, opTransport));
77 : }
78 0 : return HCCL_SUCCESS;
79 : }
80 :
81 0 : HcclResult CollRunAlltoAllVFullMesh::CalcCommInfo(std::vector<LevelNSubCommTransport>& opTransport)
82 : {
83 0 : TransportMemType inputType = TransportMemType::RESERVED;
84 0 : TransportMemType outputType = TransportMemType::RESERVED;
85 :
86 0 : CHK_RET(CalAlltoAllFullMeshCommInfo(inputType, outputType, opTransport));
87 0 : return HCCL_SUCCESS;
88 : }
89 :
90 0 : HcclResult CollRunAlltoAllVFullMesh::KernelRun(const OpParam ¶m, ExecMem &execMem)
91 : {
92 0 : HCCL_CONFIG_INFO(HCCL_ALG, "[CollRunAlltoAllVFullMesh][KernelRun] AllToAllV fullmesh start");
93 0 : bool opbaseCopyMode = workflowMode_ == HcclWorkflowMode::HCCL_WORKFLOW_MODE_OP_BASE &&
94 0 : isAlltoAllZCopyMode_;
95 :
96 : // 构造入参
97 0 : AlltoAllVBufferInfo sendInfo;
98 0 : sendInfo.mem = opbaseCopyMode ? execMem.inputMem : algResResp_->paramInputMem;
99 0 : sendInfo.counts = &allMeshAggregationSendRecvInfo_[topoAttr_.userRank].sendCounts[0];
100 0 : sendInfo.displs = &allMeshAggregationSendRecvInfo_[topoAttr_.userRank].sendDispls[0];
101 0 : sendInfo.dataType = param.All2AllDataDes.sendType;
102 :
103 0 : AlltoAllVBufferInfo recvInfo;
104 0 : recvInfo.mem = opbaseCopyMode ? execMem.outputMem : algResResp_->paramOutputMem;
105 0 : recvInfo.counts = &allMeshAggregationSendRecvInfo_[topoAttr_.userRank].recvCounts[0];
106 0 : recvInfo.displs = &allMeshAggregationSendRecvInfo_[topoAttr_.userRank].recvDispls[0];
107 0 : recvInfo.dataType = param.All2AllDataDes.recvType;
108 :
109 0 : CHK_RET(CheckCommSize(COMM_COMBINE_ORDER, COMM_INDEX_0 + 1));
110 0 : SubCommInfo level0CommInfo = GetSubCommInfo(COMM_COMBINE_ORDER, COMM_INDEX_0);
111 :
112 : // 执行算法
113 0 : std::map<u32, std::vector<u64>> rankSendDisplsMap;
114 0 : std::map<u32, std::vector<u64>> rankRecvDisplsMap;
115 0 : if (workflowMode_ != HcclWorkflowMode::HCCL_WORKFLOW_MODE_OP_BASE || isAlltoAllZCopyMode_) {
116 0 : for (u32 i = 0; i < topoAttr_.userRankSize; i++) {
117 0 : rankSendDisplsMap.insert(std::pair<u32, std::vector<u64>>(i, allMeshAggregationSendRecvInfo_[i].sendOffset));
118 0 : rankRecvDisplsMap.insert(std::pair<u32, std::vector<u64>>(i, allMeshAggregationSendRecvInfo_[i].recvOffset));
119 : }
120 : }
121 :
122 0 : std::unique_ptr<AlgTemplateBase> pairWisePtr = AlgTemplateRegistry::Instance().GetAlgTemplate(
123 0 : TemplateType::TEMPLATE_ALL_2_ALL_V_PAIRWISE, dispatcher_);
124 0 : CHK_SMART_PTR_NULL(pairWisePtr);
125 0 : if (workflowMode_ == HcclWorkflowMode::HCCL_WORKFLOW_MODE_OP_BASE &&
126 0 : !isAlltoAllZCopyMode_) { // 单算子 && Buffer Copy模式
127 0 : CHK_RET(pairWisePtr->Prepare(sendInfo, recvInfo, execMem.inputMem, execMem.outputMem, isAlltoAllZCopyMode_,
128 : const_cast<Stream&>(param.stream), workflowMode_, rankSendDisplsMap, rankRecvDisplsMap));
129 0 : CHK_RET(RunAlltoAllTemplate(pairWisePtr, level0CommInfo));
130 0 : } else if (workflowMode_ == HcclWorkflowMode::HCCL_WORKFLOW_MODE_OP_BASE &&
131 0 : isAlltoAllZCopyMode_) {
132 0 : DeviceMem dstMem = execMem.inputMem.range(0, algResResp_->paramInputMem.size());
133 0 : CHK_RET(HcclD2DMemcpyAsync(dispatcher_, dstMem, algResResp_->paramInputMem, const_cast<Stream&>(param.stream)));
134 :
135 0 : CHK_RET(pairWisePtr->Prepare(sendInfo, recvInfo, execMem.inputMem, execMem.outputMem,
136 : isAlltoAllZCopyMode_, const_cast<Stream&>(param.stream),
137 : workflowMode_, rankSendDisplsMap, rankRecvDisplsMap));
138 0 : CHK_RET(RunAlltoAllTemplate(pairWisePtr, level0CommInfo)); // inputMem_ -> outputMem_
139 :
140 0 : DeviceMem srcMem = execMem.outputMem.range(0, algResResp_->paramOutputMem.size());
141 0 : CHK_RET(HcclD2DMemcpyAsync(dispatcher_, algResResp_->paramOutputMem, srcMem, const_cast<Stream&>(param.stream)));
142 0 : } else if (workflowMode_ == HcclWorkflowMode::HCCL_WORKFLOW_MODE_OPS_KERNEL_INFO_LIB) {
143 0 : CHK_RET(pairWisePtr->Prepare(sendInfo, recvInfo, isAlltoAllZCopyMode_, const_cast<Stream&>(param.stream),
144 : workflowMode_, rankSendDisplsMap, rankRecvDisplsMap));
145 : // 保证最新的commMesh是为该次alltoallv创建（不支持多线程）
146 0 : CHK_RET(RunAlltoAllTemplate(pairWisePtr, level0CommInfo));
147 : } else {
148 0 : HCCL_ERROR("[hcclImpl][RunAlltoAllVFullMesh]work flow mode is invalid");
149 0 : return HCCL_E_PARA;
150 : }
151 :
152 0 : HCCL_INFO("[CollRunAlltoAllVFullMesh] executor run success");
153 :
154 0 : return HCCL_SUCCESS;
155 0 : }
156 :
157 : REGISTER_EXEC("RunAlltoAllVFullMesh", AlltoAllVFullMesh, CollRunAlltoAllVFullMesh);
158 : } // namespace hccl
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