Line data    Source code

       1              : /**
       2              :  * Copyright (c) 2025 Huawei Technologies Co., Ltd.
       3              :  * This program is free software, you can redistribute it and/or modify it under the terms and conditions of
       4              :  * CANN Open Software License Agreement Version 2.0 (the "License").
       5              :  * Please refer to the License for details. You may not use this file except in compliance with the License.
       6              :  * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR IMPLIED,
       7              :  * INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY, OR FITNESS FOR A PARTICULAR PURPOSE.
       8              :  * See LICENSE in the root of the software repository for the full text of the License.
       9              :  */
      10              : 
      11              : #include "alg_template_register.h"
      12              : #include "all_reduce_ahc.h"
      13              : 
      14              : namespace hccl {
      15            0 : AllReduceAHC::AllReduceAHC(const HcclDispatcher dispatcher) : AllReduceAHCBase(dispatcher)
      16              : {
      17            0 : }
      18              : 
      19            0 : AllReduceAHC::~AllReduceAHC()
      20              : {
      21            0 : }
      22              : 
      23            0 : HcclResult AllReduceAHC::DisposeSubGroups(const u32 rank)
      24              : {
      25            0 :     CommAHCBaseInfo::DisposeSubGroups(rank, globalSubGroups_, level0SubGroups_, level1SubGroups_);
      26            0 :     return HCCL_SUCCESS;
      27              : }
      28              :  
      29            0 : HcclResult AllReduceAHC::CommAHCInfoInit()
      30              : {
      31            0 :     commAHCBaseInfo_.reset(new (std::nothrow) CommAHCAlignInfo(level0SubGroups_));
      32            0 :     CHK_SMART_PTR_NULL(commAHCBaseInfo_);
      33            0 :     CHK_RET(commAHCBaseInfo_->Init(AHCOpType::AHC_OP_TYPE_ALLREDUCE, ahcAlgOption_));
      34            0 :     return HCCL_SUCCESS;
      35              : }
      36              : 
      37            0 : HcclResult AllReduceAHC::RunInterAllReduce(const u32 rank, const std::vector<LINK> &links, 
      38              :     const std::unique_ptr<CommAHCBaseInfo> &commAHCBaseInfo)
      39              : {
      40            0 :     HCCL_INFO("[AllReduceAHC][RunInterAllReduce] begin inter AllReduce rank[%u]", rank);
      41              : 
      42              :     // 获取当前rank的组间rank
      43            0 :     u32 interRank = commAHCBaseInfo->GetInterRank(0, rank);
      44              : 
      45              :     // 创建执行算子实列
      46            0 :     std::unique_ptr<AlgTemplateBase> tempAlg;
      47            0 :     CHK_RET(commAHCBaseInfo->GetInterAlgTemplateOpInstance(AHCOpType::AHC_OP_TYPE_ALLREDUCE, tempAlg, dispatcher_, reduceAttr_,
      48              :         extendFlag_, ahcExtendPreparePara_));
      49              : 
      50            0 :     std::vector<std::vector<Slice>> interSlicesVector;
      51            0 :     std::vector<std::vector<LINK>>  interLinksVector;
      52            0 :     std::vector<u32>                logicCardList;
      53            0 :     CHK_RET(commAHCBaseInfo->CalcInterSlicesAndLinks(rank, DataUnitSize(dataType_), count_, links,
      54              :         interLinksVector, interSlicesVector, logicCardList));
      55              : 
      56            0 :     if(interLinksVector.size() != interSlicesVector.size()) {
      57            0 :         HCCL_ERROR("[AllReduceAHC][RunInterAllReduce]rank[%u] linksVector size[%llu] is no equal to slicesVector size [%u]",
      58              :             rank, interLinksVector.size(), interSlicesVector.size());
      59            0 :         return HCCL_E_INTERNAL;
      60              :     }
      61              : 
      62            0 :     for (u32 i = 0; i < logicCardList.size(); ++i) {
      63            0 :         HCCL_DEBUG("[AllReduceAHC][RunInterAllReduce] run logicCard[%u] rank[%u] interRank=%u, interLinksSize=%u",
      64              :              logicCardList[i], rank, interRank, interLinksVector[i].size());
      65            0 :         CHK_RET(RunInstance(interRank, interLinksVector[i], interSlicesVector[i], tempAlg, AHCOpType::AHC_OP_TYPE_ALLREDUCE));
      66              :     }
      67            0 :     return HCCL_SUCCESS;
      68            0 : }
      69              : REGISTER_TEMPLATE(TemplateType::TEMPLATE_ALL_REDUCE_AHC, AllReduceAHC);
      70              : }